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This document contains code for a module that performs binary addition of two 4-bit inputs (a and b) along with a carry-in bit (cin) and outputs the 4-bit sum (s) and carry-out bit (cout). It also defines signals for propagate (pg) and generate (gg) functions. A testbench is provided that applies toggling inputs to the module and monitors the outputs over time.

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Uday Kumar
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18 views2 pages

Testbench

This document contains code for a module that performs binary addition of two 4-bit inputs (a and b) along with a carry-in bit (cin) and outputs the 4-bit sum (s) and carry-out bit (cout). It also defines signals for propagate (pg) and generate (gg) functions. A testbench is provided that applies toggling inputs to the module and monitors the outputs over time.

Uploaded by

Uday Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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module cla(a,b, cin, s, cout,pg,gg);

input [3:0] a,b;


input cin;
output [3:0] s;
output cout,pg,gg;
wire [3:0] g,p,c;
assign g=a&b;
assign p=a^b;
assign c[0]=cin;
assign c[1]=g[0]|(p[0]&c[0]);
assign c[2]=g[1]|(p[1]&g[0])|(p[1]&p[0]&c[0]);
assign c[3]=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&c[0]);
assign cout=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&c[0]);
assign s=p^c;
assign pg=p[3]&p[2]&p[1]&p[0];
assign gg=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0]);

endmodule
TESTBENCH:
Module tb_cla_v;
reg [3:0] a,b;
reg cin;
wire [3:0] s;
wire cout,pg,gg;

cla.uut(.s(s),.cout(.cout),.pg(pg),.gg(gg),.a(a),.b(b),.cin(cin));
initial
begin
end
always #160 cin=~cin;
always #80 a[3]=~a[3];
always #40 a[2]=~a[2];
always #20 a[1]=~a[1];
always #10 a[0]=~a[0];
always #80 b[3]=~b[3];
always #40 b[2]=~b[2];
always #20 b[1]=~b[1];
always #10 b[0]=~b[0];
initial #330 $stop;
initial $monitor($time,\t a=%b,b=%b,cin=%b,s=%b,cout=%b,pg=%b,gg=%b,a,b,cin,s,cout,pg,gg);
end

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