Scribd
Upload
21 views

ECE 464 / ECE 520 Homework 5

This document outlines two homework questions for an ECE course. Question 1 involves completing a tutorial on an EDA wiki and including area and power numbers in the homework report. Question 2 involves designing a module that accumulates statistics on incoming data, including the number of inputs with even/odd parity and a gray code pattern. The design, testbench, timing/area reports from synthesis, and energy consumption must be submitted.

Uploaded by

Bruno Silva
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
21 views

ECE 464 / ECE 520 Homework 5

This document outlines two homework questions for an ECE course. Question 1 involves completing a tutorial on an EDA wiki and including area and power numbers in the homework report. Question 2 involves designing a module that accumulates statistics on incoming data, including the number of inputs with even/odd parity and a gray code pattern. The design, testbench, timing/area reports from synthesis, and energy consumption must be submitted.

Uploaded by

Bruno Silva
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

ECE 464 / ECE 520 Homework 5

On-line turn-in. Turn in a brief report AND the Verilog file for your design (not your test fixture or synopsys files) using wolfware. These will be checked using Code Comparison tools. If your code is substantially similar to someone elses you will both receive an academic violation for cheating. Question 1 Do Tutorial 3 on the EDA wiki for ECE 520. Include in your homework a brief outline including enough detail to indicate that you did and understood this tutorial. Specifically include area and power numbers generated. [10 points] Question 2 You are to design a module that accumulates statistics on an incoming data stream consisting of two individual bytes. The I/O to the module are as follows: input clock; \\ Clock input reset; \\ synchronous reset - active low input clear; \\ Clears statistics when high (synchronous) input [7:0] DataIn1; \\ Input Data 1 input [7:0] DataIn2; \\ Input Data 2 // all outputs are registered output [7:0] EvenParity; \\ # of data with Even parity output [7:0] GreyCode; \\ # of data with pattern 10101010 or 01010101 output overflow; \\ =1 if any of the counters above overflow, stays high until clear goes high Thus, an example of this module running might behave.... _ _ _ _ _ _ _ _ _ _| |_| |_| |_| |_| |......_| |_| |_| |_| |_ _ | |___________ 02 03 AA 03 AA 55 ..... ..... 02 03

clock clear DataIn1 DataIn2

EvenParity GreyCode Overflow

00 00 0

01 00

03 01

05 03

..... ..... .....

FF

00

Design, verify, synthesize a module that meets these specifications. Please turn in the following: A drawing of your design. A fully commented Verilog listing of your design and test fixture. (Make sure you verify the functionality of overflow.) Final report_timing summary (from Synopsys). Final area (from Synopsys) - use report_area; Total energy consumed over your simulation run. [20 points]

You might also like