Carry Skip Adder
Carry Skip Adder
Designed to improve the delay of a ripplecarry adder. Under optimal conditions, propagation is reduced by passing carry-in to carry-out Composed of cascaded full adders with additional carry logic circuitry
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The carry out = ripple carry out
module carry_skip_adder(input [1:0] X, Y, input Cin, output [1:0]S, output reg Cout, Pf); reg P[1:0]; wire C[1:0];
always @ * P[0] = X[0] ^ Y[0]; always @ * P[1] = X[1] ^ Y[1]; always @ * Pf = P[1] & P[0]; always @ * case (Pf) 1'b0: Cout = C[1]; 1'b1: Cout = Cin; endcase ripple_carry_adder RCA0(X[0], Y[0], Cin, S[0], C[0]); ripple_carry_adder RCA1(X[1], Y[1], C[0], S[1], C[1]); endmodule
module eight_bit_carry_skip(input [7:0] A,B, input Cin, output Cout, output [7:0] S); wire[2:0] C; carry_skip_adder c1(A[1:0], B[1:0], Cin, S[1:0], C[0]); carry_skip_adder c2(A[3:2], B[3:2], C[0], S[3:2], C[1]); carry_skip_adder c3(A[5:4], B[5:4], C[1], S[5:4], C[2]); carry_skip_adder c4(A[7:6], B[7:6], C[2], S[7:6], Cout); endmodule