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Pipeline Data Hazards: Example #1 - Write-Back Data Hazard

The document discusses different types of data hazards that can occur in a pipelined processor and methods to address them. Write-back hazards and read-after-write hazards are solved using forwarding to bypass data between pipeline stages. When forwarding fails due to a "negative time" dependency, stalls must be inserted. The compiler can also help avoid stalls by scheduling instructions to minimize dependencies between loads and dependent operations.

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Vardhan Roy
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210 views6 pages

Pipeline Data Hazards: Example #1 - Write-Back Data Hazard

The document discusses different types of data hazards that can occur in a pipelined processor and methods to address them. Write-back hazards and read-after-write hazards are solved using forwarding to bypass data between pipeline stages. When forwarding fails due to a "negative time" dependency, stalls must be inserted. The compiler can also help avoid stalls by scheduling instructions to minimize dependencies between loads and dependent operations.

Uploaded by

Vardhan Roy
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Patterson & Hennessy, Computer Organization and Design Chapter 6

Pipeline Data Hazards


Pipeline relies on the overlap of instruction fetch-decode-execute cycle to provide speedups in performance; Implication no longer able to assume sequential ordering of operand read/ write access.

Example #1 Write-Back Data Hazard


Consider the following code sequence, opcode DADD DSUB AND OR XOR target R1 R4 R6 R8 R10 Source#1 R2 R1 R1 R1 R1 Source#2 R3 R5 R7 R9 R11

Figure 1: Write-Back Data Hazard.


Malcolm I. Heywood CSCI3121

Patterson & Hennessy, Computer Organization and Design Chapter 6

Observations see figure 1. o All instructions following ADD use R1 where R1 value only known after ADD instruction completed; o At what point in time does R1 appear from the pipe? o When does the SUB and AND instruction require R1s value? o OR operation requires R1s value in same cycle as ADD write-back. Can we avoid R1 read-write conflict?

Forwarding (or bypassing)


Observations, o SUB instruction does not need R1 value until the next clock cycle; Solution o Provide additional routing between ALU pipe output and input; o Control logic, Extension, o Provide similar routing from memory stage (MEM) to ALU input; Why, what does this solve? Figure 2 summarizes the forwarding paths necessary to solve this example. Detects ALU output as source for decode instruction Selects ALU output as source rather than the register (specified by the instruction). Why? o ADD result (R1) actually available at the SUB Instruction Decode Cycle;

Malcolm I. Heywood CSCI3121

Patterson & Hennessy, Computer Organization and Design Chapter 6

Figure 2: Forwarding routes for avoiding data hazards in example #1.

Example #2 Write-Back Data Hazard


Consider the following code fragment, opcode DADD LOAD STORE 1. R1 of ADD to load Solve using? Solve using? 2. R1 of ADD to store 3. R4 of load to store target R1 R4 Mem[12 + R1] Source#1 R2 Mem[0 + R1] R4 Source#2 R3

What are the dependencies in this case?

Malcolm I. Heywood CSCI3121

Patterson & Hennessy, Computer Organization and Design Chapter 6

Solve using? Figure 3 summarizes the necessary forwarding paths.

Figure 3: Forwarding routes for avoiding data hazards in example #2.

Example #3 When Forwarding Fails


Consider the following code sequence, opcode LOAD DSUB AND OR Observations, o Load operation causes R1 dependency. o R1 not available until MEM stage (clock 4). o Figure 4 summarizes the problem note the case of a negative time forwarding pass. target R1 R4 R6 R8 R1 R1 R1 Source#1 Source#2 R5 R7 R9 Mem[0 + R2]

Malcolm I. Heywood CSCI3121

Patterson & Hennessy, Computer Organization and Design Chapter 6

Figure 4: When forwarding paths fail negative time. Need to introduce a stall or bubble into the pipe. Pipe / hardware INTERLOCK o Detects and inserts stalls into pipe o CPI increases by length of the stall. o Figure 5 summarizes the resulting stall cycle. Instruction 1 LD DSUB AND OR Figure 5: Case of stalled cycle IF 2 ID IF 3 EX ID IF 4 MEM Stall Stall Stall Clock 5 WB EX ID IF MEM EX ID WB MEM EX WB MEM WB 6 7 8 9

Compiler or Instruction Scheduling for Data Hazards


Objective let the compiler arrange instructions to minimize the number of stalls. Consider, 5

Malcolm I. Heywood CSCI3121

Patterson & Hennessy, Computer Organization and Design Chapter 6

o Interested in producing code that avoids pipeline stalls in the following code fragment, a=b+c d=ef

o Assume a load latency of 1 clock cycle. Dependencies between the load for variables b and c and the ADD operation. Dependencies between the load for variables e and f and the SUB operation. Solution interleave load to e and f, or Target R1 R2 R3 R4 R5 a R6 d Source(s) b c e R1, R2 f R4 R3, R5 R6 Delaying the STORE avoids stalling on LOAD for f. Forward logic of the pipe avoids delay to the final STORE. Interleave load for SUB to avoid stalling on c. Comment LOAD LOAD LOAD ADD LOAD STORE SUB STORE

Instruction

Summary
Basic Data hazards and some of their solutions identified, o Forwarding applicable providing we do not need to forward results to a point in the execution pattern before the current clock count; o Interlock automatically inserts stalls when forwarding fails; o Compiler responsible for breaking up the sequential nature of program code. By doing so data dependencies are minimized and the pipe becomes more efficient.

Malcolm I. Heywood CSCI3121

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