Scribd
Upload
466 views2 pages

Gray Code Updown Counter

This document discusses a 4-bit Gray code up-down counter. It operates similarly to a binary up-down counter but counts using Gray code instead of binary. The truth tables show the up and down counting behavior for both the binary and Gray code outputs. VHDL code is provided to implement the counter, which uses XOR gates to convert between the binary and Gray code representations on each clock cycle.

Uploaded by

vharish200
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
466 views2 pages

Gray Code Updown Counter

This document discusses a 4-bit Gray code up-down counter. It operates similarly to a binary up-down counter but counts using Gray code instead of binary. The truth tables show the up and down counting behavior for both the binary and Gray code outputs. VHDL code is provided to implement the counter, which uses XOR gates to convert between the binary and Gray code representations on each clock cycle.

Uploaded by

vharish200
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 2

Gray code up down counter

By S.Ravishankar and V.Manikandan

Concept: The reflected binary code, also known as Gray code after Frank Gray, is a binary numeral
system where two successive values differ in only one bit. It is a non-weighted code. A 4 bit gray code up down counter counts in a similar way to a normal 4 bit binary up down counter except the fact that it counts using gray code. Up count truthtable(when select bit is 1)

Down count truthtable(when select bit is 0)

Binary

Gray

Truth table: Clock 0 1 1 1 Reset X 0 1 1 Select X X 1 0 Action Circuit disabled Count=0000 Up count Down count

VHDL code library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity updown is port( clk,r:in std_logic; a:inout std_logic_vector(3 downto 0); g:inout std_logic_vector(3 downto 0)); end; architecture count of updown is begin process(clk) begin if(clk 'event and clk='1' and r='0') then a<="0000" ; g<="0000"; elsif(clk'event and clk='1' and r='1') then a<=a+"1"; end if; g(3)<=a(3); g(2)<=a(3) xor a(2); g(1)<=a(2) xor a(1); g(0)<=a(1) xor a(0); end process; end ;

You might also like