Unit 3 CSA
Unit 3 CSA
Moris Mano
INDEX
UNIT-II PPT SLIDES
Srl. No.
Lecture No.
1. Micro Programmed Control 2. Control memory 3. Address sequencing 4. Micro program Example 5. Design of control unit Hardwired control 6. Micro programmed Control
Microinstruction
- Contains a control word and a sequencing word Control Word - All the control information required for one clock cycle Sequencing Word - Information needed to decide the next microinstruction address - Vocabulary to write a microprogram
Dynamic Microprogramming
- Computer system whose control unit is implemented with a microprogram in WCS - Microprogram can be changed by a systems programmer or a user
ADDRESS SEQUENCING
Instruction code Mapping
logic
Status bits
Branch logic
MUX select
CONDITIONAL BRANCHING
Load address
MUX
Control memory
...
Status bits (condition) Condition select Next address Micro-operations
Conditional Branch
If Condition is true, then Branch (address from the next address field of the current microinstruction) else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc.
Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
MAPPING OF INSTRUCTIONS
Direct Mapping
OP-codes of Instructions ADD 0000 AND 0001 LDA 0010 STA 0011 BUN 0100 Mapping Bits
10 xxxx 010 Address 0000 0001 0010 0011 0100 ADD Routine AND Routine LDA Routine STA Routine BUN Routine Control Storage
. . .
Address 10 0000 010 10 0001 010 10 0010 010 10 0011 010 10 0100 010
ADD Routine AND Routine LDA Routine STA Routine BUN Routine
Address
0 x x x x 0 0
0 1 0 1 1 0 0
Mapping function implemented by ROM or PLA OP-code Mapping memory (ROM or PLA)
MICROPROGRAM
Computer Configuration
MUX
10 AR Address 10 PC 0 Memory 2048 x 16 0
EXAMPLE
Microinstruction Format
3 F1 3 F2 3 F3 2 CD 2 BR 7 AD
F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field
BR 00 01 10 11
Function CAR AD if condition = 1 CAR CAR + 1 if condition = 0 CAR AD, SBR CAR + 1 if condition = 1 CAR CAR + 1 if condition = 0 CAR SBR (Return from subroutine) CAR(2-5) DR(11-14), CAR(0,1,6) 0
SYMBOLIC MICROINSTRUCTIONS
Symbols are used in microinstructions as in assembly language A symbolic microprogram can be translated into its binary equivalent by a microprogram assembler. Sample Format five fields: Label:
label; micro-ops; CD; BR; AD may be empty or may specify a symbolic address terminated with a colon
Micro-ops: consists of one, two, or three symbols separated by commas CD: one of {U, I, S, Z}, where U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC
BR: AD:
one of {JMP, CALL, RET, MAP} one of {Symbolic address, NEXT, empty}
During FETCH, Read an instruction from memory and decode the instruction and update PC Sequence of microoperations in the fetch cycle:
AR PC DR M[AR], PC PC + 1 AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0
CD 00 00 00
BR 00 00 11
SYMBOLIC MICROPROGRAM
Control Storage: 128 20-bit words The first 64 words: Routines for the 16 machine instructions The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
Microops
ORG 0 NOP READ ADD ORG 4 NOP NOP NOP ARTPC ORG 8 NOP ACTDR WRITE ORG 12 NOP READ ACTDR, DRTAC WRITE ORG 64 PCTAR READ, INCPC DRTAR READ DRTAR
CD
I U U S U I U I U U I U U U U U U U U
BR
CALL JMP JMP JMP JMP CALL JMP CALL JMP JMP CALL JMP JMP JMP JMP JMP MAP JMP RET
AD
INDRCT NEXT FETCH OVER FETCH INDRCT FETCH INDRCT NEXT FETCH INDRCT NEXT NEXT FETCH NEXT NEXT NEXT
BRANCH: OVER:
STORE:
EXCHANGE:
FETCH: INDRCT:
BINARY MICROPROGRAM
Micro Routine ADD Address Decimal Binary 0 0000000 1 0000001 2 0000010 3 0000011 4 0000100 5 0000101 6 0000110 7 0000111 8 0001000 9 0001001 10 0001010 11 0001011 12 0001100 13 0001101 14 0001110 15 0001111 64 65 66 67 68 1000000 1000001 1000010 1000011 1000100 F1 000 000 001 000 000 000 000 000 000 000 111 000 000 001 100 111 110 000 101 000 101 Binary Microinstruction F2 F3 CD 000 000 01 100 000 00 000 000 00 000 000 00 000 000 10 000 000 00 000 000 01 000 110 00 000 000 01 101 000 00 000 000 00 000 000 00 000 000 01 000 000 00 101 000 00 000 000 00 000 100 000 100 000 000 101 000 000 000 00 00 00 00 00 BR 01 00 00 00 00 00 01 00 01 00 00 00 01 00 00 00 00 00 11 00 10 AD 1000011 0000010 1000000 1000000 0000110 1000000 1000011 1000000 1000011 0001010 1000000 1000000 1000011 0001110 0001111 1000000 1000001 1000010 0000000 1000100 0000000
BRANCH
STORE
EXCHANGE
FETCH
INDRCT
3 x 8 decoder 7 6 54 3 21 0
3 x 8 decoder 7 6 54 3 21 0
3 x 8 decoder 76 54 3 21 0
AND ADD DRTAC PCTAR DRTAR From From PC DR(0-10) 0 1 Multiplexers Arithmetic logic and shift unit
AC DR
Load
AC
Select
Load
AR
Clock
IR
Status F/Fs
Control Points
CPU
Microprogram
M e m o r y
Control Data IR Status F/Fs
C S A R
C S D R
C P s
CPU
- NEXT MICROINSTRUCTION
External (MAP)
MICROPROGRAM SEQUENCER
Branch, CALL Address RETURN form Subroutine In-Line
L
ADDRESS LOGIC
S1S0 00 01 10 11
Address Source CAR + 1, In-Line SBR RETURN CS(AD), Branch or CALL MAP
3 2 1 0 S1 MUX1 S0
SBR
Subroutine CALL
Incrementer
Clock
CAR
Control Storage
MUX-1 selects an address from one of four sources and routes it into a CAR
- In-Line Sequencing CAR + 1 - Branch, Subroutine Call CS(AD) - Return from Subroutine Output of SBR - New Machine instruction MAP
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL L BR field of CS
T Input I0 logic I
1
From I CPU S
1 MUX2 Select Z
Test
L(load SBR with PC) for subroutine Call S0 for next address S1 selection
CD Field of CS
Input Logic
I0I1T 000 001 010 011 10x 11x Meaning Source of Address In-Line JMP In-Line CALL RET MAP CAR+1 CS(AD) CAR+1 CS(AD) and SBR <- CAR+1 SBR DR(11-14) S1S0 00 10 00 10 01 11 L 0 0 0 1 0 0
1 I S Z
Incrementer
MUX2 Select Test Clock CAR
...
...
MICROINSTRUCTION FORMAT
Information in a Microinstruction - Control Information - Sequencing Information - Constant Information which is useful when feeding into the system These information needs to be organized in some way for - Efficient use of the microinstruction bits - Fast decoding Field Encoding - Encoding the microinstruction bits - Encoding slows down the execution speed due to the decoding delay - Encoding also reduces the flexibility due to the decoding hardware