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Assignment 5

This assignment is due on October 11. Students are advised to contact the TA's for help with the assignment in the next two weeks. The assignment involves: 1. Simulating a 31-stage ring oscillator in the TSMC 180nm technology with and without substrate resistance and observing the difference in oscillation frequency. 2. Implementing a 3-8 decoder including: designing the pad layouts, sizing transistors to meet input/output capacitance specs, floorplanning, drawing unique gate layouts, completing the decoder layout, extracting a SPICE netlist, and simulating for correct function and delay.

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24 views

Assignment 5

This assignment is due on October 11. Students are advised to contact the TA's for help with the assignment in the next two weeks. The assignment involves: 1. Simulating a 31-stage ring oscillator in the TSMC 180nm technology with and without substrate resistance and observing the difference in oscillation frequency. 2. Implementing a 3-8 decoder including: designing the pad layouts, sizing transistors to meet input/output capacitance specs, floorplanning, drawing unique gate layouts, completing the decoder layout, extracting a SPICE netlist, and simulating for correct function and delay.

Uploaded by

Vineesh Vs
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 5: EE 671

Madhav P. Desai September 26, 2012


This assignment is due on October 11. For assistance, you may contact the TAs of this course for any help that you need. The TAs will be present in the VLSI laboratory on Monday, Wednesday, Thursday and Friday afternoons in the next two weeks. Please start working early so that you are likely to nish on time (and learn something). 1. In the TSMC 180nm technology, consider a 31-stage ring oscillator in which each inverter is sized as 20/10. To model the substrate/well, assume that there is a resistance of value R connected between each MOSFET body terminal and VSS or VDD as the case may be. Simulate this ring oscillator for R = 0 and R = 1M and observe the oscillation frequency. Comment on the dierence, if any. 2. Implement the 3-8 decoder discussed in class. (a) The pads are to be 70 70 and are constructed using all the metal layers from M1 to M6 (with contacting between the metal layers: use an array of 2X2 contacts). The VDD pad sits on top of an N-well and N+ diusion and the lowest level metal in the pad is connected to the N+ diusion. The VSS pad sits on top of a P+ diusion and the lowest level metal in the pad is connected to this P+ diusion. (b) The input capacitance of the decoder is to be at most 100f f and the load to be driven by the decoder is to be 10pf . (c) Identify the circuit for the decoder and the transistor sizes in all the gates that you will be using (as you did in the earlier assignment). (d) Sketch the oorplan of your layout. Identify the horizontal and vertical pitches in the regular structures. (e) Sketch the stick diagrams of the unique gates in your layout. (f) Draw the layout of the decoder. (g) Extract a SPICE netlist from your decoder layout. (h) Simulate the netlist to ensure that your decoder functions as expected. Is the delay as you expected?

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