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PHASE-LOCKED
Loop CIRCUIT
DESIGN
DAN H. WOLAVERPRENTICE HALL
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PHASE-LOCKED Loop
Cirncurr DESIGN
Dan H. Wolaver
Worchester Polytechnic Institute
a
Prentice Hall
Englewood Cliffs, New Jersey 07632Library of Congress Catalaging-in-Publication Data
Wolaver, Dan H.
Phase-locked loop circuit design / Dan H. Wolaver.
B. cm. ~- (Prentice Hall advanced reference series)
Includes bibliographical references and index,
ISBN 0-13-662743-9
1. Phase-locked loops. 2. Electronic circuit design. I. Title.
‘TK7872.P38H65 1991
621.381'5--de20 90-23685
Crp
Editorial/production supervison
and interior design: Rick DeLorenzo
Cover design: Wanda Lubelska Design
Manufacturing buyers: Kelly Behr and Susan Brunke
Acquisitions Editor: Karen Gettman
Prentice Hall Advanced Reference Series
Prentice Hall Biophysics and Bioengineering Series
© 1991 by Prentice-Hall, Inc.
A Division of Simon & Schuster
Englewood Cliffs, New Jersey 07632
All rights reserved. No part of this book may be
reproduced, in any form or by any means,
without permission in writing from the publisher.
Printed in the United States of America
0987654321
ISBN 0-13-662743-9
Prentice-Hall International (UK) Limited, London
Prentice-Hall of Australia Pty. Limited, Sydney
Prentice-Hall Canada Inc., Toronto
Prentice-Hall Hispanoamericana, S.A., Mexico
Prentice-Hall of India Private Limited, New Delhi
Prentice-Hall of Japan, Inc., Tokyo
Simon & Schuster Asia Pte. Ltd., Singapore
Editora Prentice-Hall do Brasil, Ltda., Rio de Janeiro
CONTENTS
PREFACE
INTRODUCTION
Ll Carrier Recovery 2
1-2 Clock Recovery 3
1-3 Tracking Filter 3
1-4 Frequency Demodulation 4
1-5 Phase Demodulation 5
1-6 Phase Modulation 5
1-7 Frequency Synthesis 6
1-8 Organization of Text 7
1-9 Other Information on Phase-Locked Loops 7
PHASE-LOCKED LOOP BASICS
2-1 Phase-Locked Loop Characteristics 9
2-2 Phase Detector Characteristics 11vi
Contents
2-3 VCO Characteristics 11
2-4 Linear Model of PLL 13
2-5 Static Phase Error 14
2-6 PLL Bandwidth 15
2-7 Loop Filter 20
2-8 Static Phase Error with Loop Filter 22
LOOP FILTERS 25
3-1 Active Loop Filter 26
3-2 Static Phase Error with Active Loop Filter 28
3-3 Alternative Active Loop Filter Designs 29
3-4 Active Loop Filter Offsets 31
3-5 PLL Frequency Response 32
3-6 PLL Step Response 36
3-7 Limited Loop Filter Bandwidth 38
3-8 Phase Error Response 43
PHASE DETECTORS 47
4-1 Four-Quadrant Multipliers 47
42 Gilbert Multiplier 50
43 Phase Detector Figure of Merit 52
4-4 Double Balanced Multiplier 52
4-5 Triangular Phase Detector Characteristic 54
4-6 Exclusive-OR Phase Detector 55
47 Two-State Phase Detector 59
48 Three-State Phase Detector 61
4-9 Z-State Phase Detector 65
4-10 Sample-and-Hold Phase Detector 67
411 Extended Range: Frequency Division 68
4-12 Extended Range: n-State Phase Detector 68
4-13 Modified Phase Detector Characteristic 75
VOLTAGE-CONTROLLED OSCILLATOR Bt
5-1 Properties of VCOs 81
5-2 Voltage-Controlled Multivibrators 83
5-3 Resonant VCOs 86
5-4 Modulation Bandwidth 91
5-5 Q of the Resonant Circuit 92
5-6 Crystal VCOs 94
5-7 Injection in Multivibrator VCOs 97
Contents
5-8 Injection in Resonant VCOs_ 100
5-9 PLL Behavior with Injection 102 .
5-10 Spectral Purity 105
6. NOISE 107
6-1 Power Spectral Density 107
6-2 Noise Bandwidth 109
6-3 Noise-Induced Phase 111
6-4 Output Phase Noise Due to Input Noise 116
6-5 VCO Phase Noise 120
6-6 Output Phase Noise Due to VCO Noise 126
6-7 Output Phase Noise Due to Both Nosie
Sources 128
6-8 Cycle Slips 131
7. MAINTAINING LOCK : 135
71 Hold-In Range 135
7-2 Input Frequency Deviation Aw; 136
7-3 Lock-In Frequency w, 138
7-4 Transfer Function from Aw; to @, 142
75 Handling a Frequency Step 143
7-6 Handling a Frequency Ramp = 145
7-7 Handling Sinusoidal FM 148
7-8 Handling Random FM 151
8. LOCK ACQUISITION 155
8-1 Self Acquisition: Active Loop Filter 157
8-1-1 Pull-In Voltage v, 157
8-1-2 Pull-In Time T, 160
8-1-3 Pull-In Range w, 163
8-2 Self Acquisition: Passive Loop Filter 164
8-3 Acquisition with a Pole at w; 168
8-4 Acquisition with a Three-State PD 171
8-5 Aided Acquisition with a Three-State PD 174
8-6 Rotational Frequency Detector 177
9. MODULATION AND DEMODULATION 185
9-1 Phase Modulation 185
9-1-1 Bandwidth, Phase and Frequency
Ranges 186viii
10.
9-1-2 Spurious Modulation 187
9-1-3 Spurious Modulation with a Pole at
@, 189
9-2 Phase Demodulation 192
9-3 Phase Demodulation with No Carrier 195
9-3-1 Squaring Loop 196
9-3-2 Remodulator and Costas Loop 200
9-4 Frequency Modulation 202
9-5 Frequency Demodulation 205
CLOCK RECOVERY
10-1 Data Formats and Spectra 212
10-2 Conversion from NRZ and RZ Data . 213
10-3 Phase Detectors for RZ Data 216
10-4 Pattern-Dependent Jitter 218
10-5 Phase Detectors for NRZ Data 220
10-6 Offset Jitter 220
10-7 Jitter Accumulation 230
FREQUENCY SYNTHESIZERS
11-1 Single-Loop Synthesizer 239
11-2 Choosing the Bandwidth K 240
11-3 Synthesizer with Mixer 241
11-4 Spurious Modulation 242
11-5 Divided Output 248
11-6 Pull-In Time 248
11-7 Multiplexed Output 250
11-8 Multiple-Loop Synthesizer 250
11-9 Phase Noise 252
11-10 Prescaling 257
LIST OF SYMBOLS
INDEX
Contents
2n
239
260
261
PREFACE
This book provides a practical introduction to phase-locked loops for the practicing
electrical engineer. Beginning with basic principles, it covers applications such as clock
recovery, FM and PM modulation and demodulation, and frequency synthesis. Each
application includes the development of design formulas for the system parameters—
bandwidth, noise, acquisition range and speed, dynamic range, stability, and accuracy.
While providing the necesssary system theory, the book’s main emphasis is the practical
realization of phase-locked loop circuits. For example, it addresses stray coupling, current
limitations, offset voltages, and bandwidth limitations. Many alternative circuits are
described with extensive use of examples and figures.
The experienced specialist in phase-lock loops will find material here that extends
his knowledge. Several new digital phase detectors are described. The choice between
lock acquisition techniques is clarified. The often confounding problem of injection
locking is treated in depth.
To simplify the connection between phase-locked loop theory and design, the text
abandons the traditional natural frequency , and damping factor { of control theory. The
parameter w, is often misleading since it has little relation to system behavior in a highly
damped system. The parameters used in this text are the bandwidth K and the zero
frequency w,, which give a better description of system behavior. K is the 3-dB bandwith
for all dampings except those near instability. The value of w in relation to K essentially* Preface
gives the damping through the expression £ = 0.5/K/w>, and it is closely tied to the
circuit elements. Both K and «, are clearly evident in Bode plots of frequency responses,
providing a visual link between design and petformance.
This text has been used for a course on phase-locked loop circuit design at the
graduate level, where it has served those with immediate applications for: phase-locked
loops and those who wish to consolidate their facility with circuit design in general. The
study of phase-locked loops is an excellent vehicle for putting to use various disciplines of
electrical engineering: communication theory, control theory, signal analysis, noise
characterization, design with transistors and op amps, digital circuit design, and nonlinear
circuit analysis.
The author is grateful to his students at Worcester Polytechnic Institute for their help
in refining the contents of this book. The work assignments at Bell Telephone Laborato-
ties and at Tau-tron, Inc. have provided the anvil on which to shape his understanding of
phase-locked loops. The author has found the study and design of phase-locked loops to
be a rich area for providing challenges to innovation and solutions to practical problems. It
is his hope that this text will shorten the path for other design engineers and help them to
enjoy the discovery and creativity available in phase-locked loop circuit design.
INTRODUCTION
Phase-locked loops are used primarily in communication applications. For example,
they recover clock from digital data signals, recover the carrier from satellite transmission
signals, perform frequency and phase modulation and demodulation, and synthesize exact
frequencies for receiver tuning. In this chapter we look at the basic principles of phase-
locked loop operation in these applications. The approach here is informal and non-
numeric in order to provide a quick overview. The intent is to provide heuristic descrip-
tions that will raise questions to be answered in the following chapters.
A phase-locked loop (PLL) is basically an oscillator whose frequency is locked onto
some frequency component of an input signal v;. This is done with a feedback control
loop, as shown in Fig. 1-1. The frequency of this component in v; is «; (in rad/s), and its
phase is 6;. The oscillator signal v, has a frequency w, and a phase 6,. The phase detector
(PD) compares 0, with 0,, and it develops a voltage vz proportional to the phase
difference. This voltage is applied as a control voltage v, to the voltage-controlled
oscillator (VCO) to adjust the oscillator frequency @,. Through negative feedback, the
PLL causes w, = w;, and the phase error is kept to some (preferably small) value. Thus,
both the phase and the frequency of the oscillator are ‘‘locked’’ to the phase and the
frequency of the input signal.