Power On Sequence Introduction
Power On Sequence Introduction
OUTLINE
General Power On Sequence Power On Sequence (P5Q3) Power On Sequence (M3N78-VM) No Power Problem Debug Point
Cap./ Res.
PANNEL
0
PSON + 5 GND GND - 12V + 3V + 3V + 3V
IT8282
PSON Pull low circuit
PWRBTN 0
PSON 0
Super I/O
South Bridge
+5 +5 -5
+ 12 5VSB PWOK
CPU SOCKET
(2)
CPURST
(5)
PG1 IDERST S
Circuit
PWROK (3) (4) PCIRST
IDE SLOT
North Bridge
PCI SLOT
Circuit
PSON (1) PANNEL PWRBTN
South Bridge
GMCH
USER PRESS CRTL+ATL+DEL
O_PWROKO_PWROK_NB 7 7
Super I/O
3 O_PWRBTNIN# 2 O_RSMRST# O # O_KB_RST# O # 5 S_SLPS S 5 S_SLPS S 4 O_PWRBTN O 7 O_PWROK O
EPU
User press Rest button RSTCON#
P_VRM_GD 7
S_TRCRST#
User clear CMOS
ICH10R
8 S_PLTRST#
VCORE
S_PCIRST# 8
CPU
H_CPUPWRGD H CPUPWRGD
LAN
Power On Sequence(M3N78-VM)
14. CPU_RST# 13. PCI_RST#
CPU
12. CPU_PWROK# 10. 1.2VHT_EN 9. VCORE_PG 13. PCIE_RST#
8. VCORE_EN
11
.PWR ROK_SB
.SIO_ _PWRBTN# #
.SIO_ _RST#
.SU USB#
.SU USC#
.RS SMRST#
VRM
6. 12V
6. 3V
6. 5V
ATX Power
5. PSON#
SIO ITE8712F
PCIE X16 C 6
13.PCIERST#
IDE Port
11. IDE_RST#
2. PWR_BTN#
Thank You!