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R09-Advanced Computer Architecture

The document appears to be an exam paper from Jawaharlal Nehru Technological University Hyderabad for their M.Tech II - Semester examinations in Advanced Computer Architecture. The exam paper contains 8 questions and students are instructed to answer any 5 questions. The questions cover topics related to computer architecture including challenges in instruction set architecture, implementation technologies, data addressing modes, pipelining, cache performance optimizations, instruction level parallelism, symmetric shared memory architecture, cache coherence protocols, cluster computing, VLIW, RISC, and thread level parallelism.

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Yerri Swamy
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102 views

R09-Advanced Computer Architecture

The document appears to be an exam paper from Jawaharlal Nehru Technological University Hyderabad for their M.Tech II - Semester examinations in Advanced Computer Architecture. The exam paper contains 8 questions and students are instructed to answer any 5 questions. The questions cover topics related to computer architecture including challenges in instruction set architecture, implementation technologies, data addressing modes, pipelining, cache performance optimizations, instruction level parallelism, symmetric shared memory architecture, cache coherence protocols, cluster computing, VLIW, RISC, and thread level parallelism.

Uploaded by

Yerri Swamy
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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R09
Code No: D5803 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.TECH II - SEMESTER EXAMINATIONS, APRIL/MAY 2012 ADVANCED COMPUTER ARCHITECTURE
(COMPUTER SCIENCE AND ENGINEERING)

Time: 3hours Answer any five questions All questions carry equal marks --1.a) b) 2.a) b) 3.a) b) 4.

Max. Marks: 60

Discuss the challenges faced by the computer architect of ISA. Give a short note on implementation technologies for computer. Explain various data addressing modes. Differentiate between packed decimal and unpacked decimal. Discuss the implementation of five-stage pipeline. Explain advanced optimizations of cache performance.

What is instruction level parallelism? Discuss the basic compiler techniques for exposing instruction level parallelism. Write about symmetric shared memory architecture. Describe the basic schemes for enforcing coherence.

5.a) b) 6. 7. 8.

Explain in detail directory based cache coherence protocols. What is a cluster? Explain the process of designing clusters. Write short notes on the following: a) VLIW b) RISC c) Thread level parallelism.

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