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A0601 Digital System Design

The document is an exam paper for a digital system design course covering topics such as flip-flops, sequential circuits, fault testing, and PLAs. It contains 8 questions: 1) Draw the state diagram and ASM chart for a JK flip-flop and discuss ASM charts. 2) Design a combinational circuit using a ROM to square a 3-bit input number. 3) Explain how to design sequential circuits using FPGAs and define fault types with examples. 4) Explain the PODEM algorithm for fault testing and transition count testing. 5) Define a diagnosable sequential machine and how to construct it. 6) Give the PLA realization for two

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Ravula Venkatesh
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364 views2 pages

A0601 Digital System Design

The document is an exam paper for a digital system design course covering topics such as flip-flops, sequential circuits, fault testing, and PLAs. It contains 8 questions: 1) Draw the state diagram and ASM chart for a JK flip-flop and discuss ASM charts. 2) Design a combinational circuit using a ROM to square a 3-bit input number. 3) Explain how to design sequential circuits using FPGAs and define fault types with examples. 4) Explain the PODEM algorithm for fault testing and transition count testing. 5) Define a diagnosable sequential machine and how to construct it. 6) Give the PLA realization for two

Uploaded by

Ravula Venkatesh
Copyright
© Attribution Non-Commercial (BY-NC)
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Code No: A0601,A3801,A5701 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech I- Semester Supplementary Examinations September, 2010 DIGITAL SYSTEM DESIGN (COMMON TO DIGITAL SYSTEMS & COMPUTER ELECTRONICS, DIGITAL ELECTRONICS & COMMUNICATION SYSTEMS, VLSI SYSTEM DESIGN) Time: 3hours Max.Marks:60 Answer any five questions All questions carry equal marks --1.a) b) 2.a) b) 3.a) b) Draw the state diagram, state table & ASM chart for a JK Flip-Flop. Discuss the salient features of ASM charts. Design a combinational circuit using a ROM. The circuit accepts a 3 bit number and generates an output binary number equal to the square of the input number. How a sequential circuit can be designed using FPGA? What are the different types of faults and give some examples for each type? Find the faults at e and h of the following circuit shown in figure using Boolean difference method.

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4.a) b) 5. 6.

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What is PODEM? Explain how PODEM algorithm is used to test faults. How a transition count is used to test faults? Define a diagnosable sequential machine and how it can be constructed. Give the PLA realization of the following functions using a PLA with 5 inputs, 4 outputs and 8 AND gates. f1 ( A, B, C , D, E ) = m ( 0,1, 2,3,11,12,13,14,15,16,17,18,19, 27, 28, 29,30,31)
f 2 ( A, B, C , D, E ) = m ( 4,5, 6, 7,8,9,10,11, 20, 21, 22, 23,30 )

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7. 8.a) b)

What are the different faults present in PLA and how to test these faults? Draw the basic model form of NOR S-R latch and explain its function with truth table. Give a state assignment without critical races to the following asynchronous machine shown in figure below.

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