C28x Event Manager

Introduction
Now it is time to discuss one of the most powerful hardware modules of the C28x, called the Event Manager (EV). An EV is a unit that is able to deal with different types of time-based procedures. The core of this manager is a little bit similar to the DSPs core timer units Timer 0, 1 and 2. Although the Event Manager Timer units are also called "Timer 1, 2, 3 and 4", these timers are totally independent of the three core timers. So please do not mix them up! From now, when we speak of a timer unit, we have to clarify if it is a Core timer or an Event Manager timer! The Event Manager Timer unit is a 16-bit counter/timer unit, whereas a Core Timer is a 32-bit register. The most important difference between the Event Manager and the Core timers is its input/output system. An EV is able to produce hardware signals directly from an internal time event. Thus this unit is most often used to generate time based digital hardware signals. This signal is a digital pulse with binary amplitude (0, 1). With the help of the EV-logic we can modify the frequency and/or the pulse width of these output signals. When we apply an internal control scheme to modify the shape of the signals during run time, we call this Pulse Width Modulation (PWM). PWM is used for two main purposes: Digital Motor Control (DMC) Analogue Voltage Generator

We will discuss these two main areas a little bit later. The C28x is able to generate up to 16 PWM output signals. The Event Manager is also able to perform time measurements based on hardware signals. With the help of 6 edge detectors, called Capture Units we can measure the time difference between two hardware signals to determine the speed of a rotating shaft in rotations per minute. The third part of the Event Manager is called Quadrature Encoder Pulse unit (QEP). This is a unit that is used to derive the speed and direction information of a rotating shaft directly from hardware signals from incremental encoders or resolvers. The C28x is equipped with two Event Managers, called EVA and EVB. These are two identical hardware units; two 16-bit timers within each of these EVs generate the time base for all internal operations. In case of EVA the timers are called General Purpose Timer T1 and T2, in case of EVB they are called T3 and T4. This module includes also two lab-exercises Lab5 and Lab5A based on the eZdsp and the Zwickau Adapter board. To perform Lab5A you will need a simple analogue oscilloscope.

DSP28 - Event Manager

5-1

Module Topics

Module Topics

C28x Event Manager..................................................................................................................................5-1 Introduction .............................................................................................................................................5-1 Module Topics..........................................................................................................................................5-2 Event Manager Block Diagram ...............................................................................................................5-3 General Purpose Timer............................................................................................................................5-4 Timer Operating Modes ...........................................................................................................................5-5 Interrupt Sources .....................................................................................................................................5-6 GP Timer Registers..................................................................................................................................5-7 GP Timer Interrupts...............................................................................................................................5-12 Lab 5: Lets play a tune! ........................................................................................................................5-14 Event Manager Compare Units .............................................................................................................5-20 Capture Units.........................................................................................................................................5-31 Quadrature Encoder Pulse Unit (QEP) .................................................................................................5-36 Lab 5A: Generate a PWM sine wave .....................................................................................................5-39 Optional Exercise...................................................................................................................................5-50

5-2

DSP28 - Event Manager

Event Manager Block Diagram

Event Manager Block Diagram

Each Event Manager is controlled by its own logic block. This logic is able to request various interrupt services from the C28x PIE unit to support its operational modes. Two external input signals TCLKINA and TDIRA are optional control signals and are used in some specific operational modes. A unique feature of the Event Manager is it ability to start the Analogue to Digital Converter (ADC) from an internal event. A large number of common microprocessors would have to request an interrupt service to do the same the C28x does this automatically. We will use this feature in the next module! The GP Timers 1 and 2 are two 16-bit timers with their own optional output signals T1PWM/T1CMP and T2PWM/T2CMP. We can also use the two timers for internal purposes only. Recall: to use any of the C28x units we have to set the multiplex registers for the I/O ports accordingly! Compare Unit 1 to 3 are used to generate up to 6 PWM signals using GP Timer 1s time base. A large number of technical applications require exactly 6 control signals, e.g. three phase electrical motors or three phase electrical power converters. Three independent capture units CAP1, 2, and 3 are used for speed and time estimation. An incoming pulse on one of the CAP lines will take a time stamp from either GP Timer 1 or 2. This time stamp is proportional to the time between this event and the previous one. The QEP-unit redefines the 3 input lines CAP1, 2, and 3 to be used as sensed edge pulses (QEP1, 2) and a zero degree index pulse (QEPI1) for an incremental encoder.

Event Manager Block Diagram (EVA)

Reset PIE

EV Control Registers / Logic GP Timer 1 Compare GP Timer 1 Data Bus Compare Unit 1 Compare Unit 2 Compare Unit 3 GP Timer 2 Compare GP Timer 2 MUX Capture Units

TCLKINA / TDIRA ADC Start T1PWM_T1CMP

Output Logic

PWM Circuits Output Logic PWM Circuits Output Logic PWM Circuits Output Logic Output Logic
CLK DIR

PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 T2PWM_T2CMP

QEP Circuit
CAP1/QEP1 CAP2/QEP2 CAP3/QEPI1
5-2

DSP28 - Event Manager

5-3

General Purpose Timer

General Purpose Timer

The central logic of a General Purpose Timer is its Compare Block. This unit continually compares the value of a 16-bit counter (TxCNT) against two other registers: Compare (TxCMPR) and Period (TxPR). If there is a match between counter and compare, a signal is sent to the output logic to switch on the external output signal (TxPWM). If counter matches period, the signal is switched off. This is the basic operation in asymmetric mode. The second basic operating mode - symmetric mode will be explained a little bit later. Register GPTCONA controls the shape of the physical output signal. The timers clock source is selectable to be an external signal (TCLKIN), the QEP-unit or the internal clock. TxCON-bits5 and 4 control the multiplexer. In case of internal clock selection the clock is derived from the high-speed clock prescaler (HSPCLK). When you calculate the desired period you will have to take into account the setup of register HISPCP! To adjust the period of a General Purpose Timer one can use an additional prescaler (TPS, TxCON2-0), which gives a scaling factor between 1 and 128. The direction of counting depends on the selected operation mode.

General-Purpose Timer Block Diagram (EVA)

Internal (HSPCLK) TPS 2-0 TxCMPR . 15 - 0 Shadowed TxCON . 10 - 8

Clock Prescaler
M U X

Compare Register
GPTCONA

TxCNT . 15 - 0 External QEP

16 - Bit Timer Counter

Compare Logic Period Register

Shadowed TxPR . 15 - 0

Output Logic

TxPWM_ TxCMP

TCLKS 1-0 TxCON . 5 - 4

Note: x = 1 or 2

5-4

Another unique feature of the C28x is its shadow functionality of operating registers, in the case of GP Timers 1 and 2 available for compare register and period register. For some applications it is necessary to modify the values inside a compare or period register every period. The advantage of the background registers is that we can prepare the values for the next period in the previous one. Without a background function we would have to wait for the end of the current period, and then trigger a high priorized interrupt. Sometimes this principle will miss its deadline

5-4

DSP28 - Event Manager

Timer Operating Modes

Timer Operating Modes

Continuous-Up Counting Mode
(Used for Asymmetric PWM Waveforms)

This example: TxCON.3-2 = 00 (reload TxCMPR on underflow) TxCON.3TxPR = 3 Seamless counting continues TxCMPR = 1 (initially) Up count period is TxPR+1 Prescale = 1
CPU writes a 2 to compare reg. buffer anytime here TxCMPR=2 is loaded here TxCMPR=2 3 2 1 1 0 0 2 1 0 3 2 3

TxCNT Reg. TxPWM/TxCMP (active high) CPUCLK

5-5

The slides give two examples of the two most used operating modes. Note: There are two more modes see data sheet.

Continuous-Up/Down Counting Mode

(Used for Symmetric PWM Waveforms)

This example: TxCON.3-2 = 01 (reload TxCMPR on underflow or period match) TxCON.3TxPR = 3 Seamless up/down repetition TxCMPR = 1 (initially) Up/down count period is 2*TxPR 2*TxPR Prescale = 1
TxCMPR loads with a 1 3 2 1 2 1 0 1 2 TxCMPR loads with a 2 3 2 1 0 TxCMPR loads with a 1

TxCNT Reg. TxPWM/TxCMP (active high) CPUCLK

5-6

DSP28 - Event Manager

5-5

Interrupt Sources

Interrupt Sources
Each of the two timers of Event Manager A (EVA) is able to generate four types of interrupt requests: timer underflow (counter equals zero), timer compare (counter equals compare register), timer period (counter equals period register) and timer overflow (counter equals 0xFFFF not shown on slide). The slide also shows two options for the physical shape of the output signal (TxPWM) -active high and active low. The two options not shown are forced low and forced high. All four options are controlled by register GPTCONA.

Generated Outputs and Interrupts

PWM period #2 CPU Changes Period Reg. Buffer anytime here PWM period #1 New Period is Auto-loaded on Underflow here

Timer Counter Value

Comp2 Comp1

TxCMP/TxPWM (active high) TxCMP/TxPWM (active low)

Compare Ints Period Ints Underflow Ints

5-7

The example on the slides assumes Counting up/down Mode and that the timer starts with value Comp1 loaded into TxCMPR and period #1 in TXPR. At some point in period 2 our code changes the value in TXCMPR from Comp1 to Comp2. Thanks to the compare register background (or shadow) function this value is taken into foreground with the next reload condition. This leads to the new shape of the output signal for period 3. Somewhere in period 3 our code modifies register TxPR preparing the shape of period 4.The answer is the PIE (Peripheral Interrupt Expansion)-unit. Please note that we have two points for Compare Interrupts within each period. Question: How do we distinguish between them? When we go through all timer control registers on the next pages please remember this question. There must be a way to specify whether we are in the first or second half of a period.

5-6

DSP28 - Event Manager

GP Timer Registers

GP Timer Registers
To set up an Event Manager Timer we have to configure five registers per timer. If wed like to use one or more timer interrupt sources, then we have to set up a few more registers. The next slides are going through the registers step by step, at the end a lab exercise is waiting for you!

Register
T1CNT T1CMPR T1PR

GP Timer Registers
Address Description
0x007400 0x007401 0x007402 0x007403 0x007404 0x007405 0x007406 0x007407 0x007408 0x007500 0x007501 0x007502 0x007503 0x007504 0x007505 0x007506 0x007507 0x007508 General Purpose Timer Control Register A Timer 1 Counter Register Timer 1 Compare Register Buffer Timer 1 Period Register Buffer Timer 1 Control Register Timer 2 Counter Register Timer 2 Compare Register Buffer Timer 2 Period Register Buffer Timer 2 Control Register General Purpose Timer Control Register B Timer 3 Counter Register Timer 3 Compare Register Buffer Timer 3 Period Register Buffer Timer 3 Control Register Timer 4 Counter Register Timer 4 Compare Register Buffer Timer 4 Period Register Buffer Timer 4 Control Register
5-8

GPTCONA

EVA

T1CON T2CNT T2CMPR T2PR T2CON GPTCONB T3CNT T3CMPR T3PR

EVB

T3CON T4CNT T4CMPR T4PR T4CON

EXTCONA 0x007409 / EXTCONB 0x007509 ;Extension Control Register

GP Timer Control Register A (EVA)

GPTCONA @ 0x007400

Upper Byte:
Timer 2 Compare Trip Enable T2CTRIPE (if EXTCONA[0]=1)
0 = disable 1 = enable

Timer 1 Compare Trip Enable T1CTRIPE (if EXTCONA[0]=1)

0 = disable 1 = enable

15
reserved

14
T2STAT

13
T1STAT

12
RESERVED

11
RESERVED

10-9
T2TOADC

8-7
T1TOADC

GP Timer Status (read-only)

0 = counting down 1 = counting up

ADC start by event of GP Timer x

00: no event starts ADC 01: setting of underflow interrupt flag 10: setting of period interrupt flag 11: setting of compare interrupt
5-9

DSP28 - Event Manager

5-7

GP Timer Registers

GP Timer Control Register GPTCONA

Bits 14 and 13 are status bits used to report if the timer is counting up or down. Bits 10 to 7 are used to perform the automatic start of the ADC from the specified timer event. Bits 3 to 0 define the shape of the output signal. Bit 6 is used to enable the two physical output signals for timer 1 and timer 2 simultaneously. Note: There is an enhanced operating mode available. This extended mode is switched on by setting bit 0 in register EXTCONA to 1. In this case the definition of some of the register bits will change. Bit 6 is no longer used; instead bits 5 and 4 are used to enable/disable the output signals separately for timer 1 and timer2. Bits 12 and 11 are now used to enable a new power electronic safety feature called Timer Compare Trip. We will not go into these extended operating modes during this tutorial, so just treat all these new control bits as reserved. Reserved means for a write operation into registers you can set the bit position as a dont care.

GP Timer Control Register A (EVA)

Lower Byte:
GPTCONA @ 0x007400 Timer 2 Compare Output Enable T2CMPOE (if EXTCONA[0]=1)
0 = disable (hi-Z) (hi1 = enable
6
TCOMPOE

Timer 1 Compare Output Enable T1CMPOE (if EXTCONA[0]=1)

0 = disable (hi-Z) (hi1 = enable

5
RESERVED

4
RESERVED

3-2
T2PIN

1-0
T1PIN

TxPWM/TxCMP Output Pin Conditioning Compare Output Enable

(reserved when EXTCONA[0]=1) 0 = all disable (hi-impedance) (hi1 = all enable 00: forced low 01: active low 10: active high 11: forced high

5 - 10

Timer Control Register TxCON

Next, we have to set up the individual timer control registers. The layout is shown on the next two slides. Bits 15 and 14 are responsible for the interaction between the timer unit and a command executed by the JTAG-Emulator unit. We will find this control bits pair for all other peripheral units of the C28x. It is very important to be able to set up a definite behaviour when, for example, the execution of our code hits a breakpoint. In case of real hardware connected to the outputs it could be very dangerous to stop the outputs in a random fashion. For the timer unit we can specify to stop its operation immediately, at the end of a period, or not at all. Of course this depends on the hardware project, for our lab exercises its good practice to stop immediately.

5-8

DSP28 - Event Manager

GP Timer Registers

Timer Control Register (EVA)

T1CON @ 0x007404 / T2CON @ 0x007408

Upper Byte:
15 FREE 14 SOFT 13 reserved 12 11 10 TPS2 9 TPS1 8 TPS0

TMODE1 TMODE0

Emulation Halt Behavior 00 = stop immediately 01 = stop at end of period 1x = free run (do not stop)

Timer Clock Prescale

000: 1 001: 2 010: 4 011: 8 100: 16 101: 32 110: 64 111: 128

Count Mode Select

00 = stop/hold 01 = continuous-up/down 10 = continuous-up 11 = directional-up/down
5 - 11

Bits 12-11 select the operation mode. Weve discussed the two most important modes before; the two remaining modes are the Directional Up/Down mode and the Stop/Hold mode. The first mode uses an external input (TDIRA) to specify the counting direction; the latter just halts the timer in its current status, no re-initialization needed to resume afterwards. Bits 10 to 8 are the input clock prescaler to define another clock division factor. Recall that the counting frequency is derived from:

The external oscillator (30MHz) The internal PLL-status (PLLCR: multiply by 10/2 = 150 MHz) The High speed clock prescaler (HSPCP = divide by 2: 75 MHz) and The Timer Clock Prescale factor (1 to 128)

This gives us the option to specify the desired period for a timer. For example, to setup a timer period of 100 milliseconds, we can use this calculation: Timer input pulse = (1/ext_clock_freq) * 1/PLL * HISPCP * Timer TPS 1,7067 s = (1/ 30 MHz) 100 ms / 1,7067 s = 58593. Load TxPR with 58593 to set the timer period to 100 milliseconds. * 1/5 * 2 * 128

DSP28 - Event Manager

5-9

GP Timer Registers

Bit 6 enables the timer operation. At the end of an initialization procedure we will have to set bit 6 to 1 to start the timer. Bits 5 and 4 select the timer clock source; Bits 3 and 2 define the point of time to reload the value out of the background register into the foreground compare register. Bit 1 is used to enable the compare operation. Sometimes youll need an internal period generator only, for these applications you can switch off the compare operation that is the generation of switch patterns for the output lines. Bits 7 and 0 are timer 2 specific bit fields. They are dont cares for register T1CON. With the help of bit 7 we can force a start of timer 1 and 2 simultaneously. In this case, both timers start if bit 6 (TENABLE) of T1CON is set. Bit 0 forces timer 2 to use period register of timer 1 as base to generate a synchronized period for timer 2 and timer 1.

Timer Control Register (EVA)

T1CON @ 0x007404 / T2CON @ 0x007408
0 = disable 1 = enable

Lower Byte:
Timer Enable
0 = timer disable 1 = timer enable

Timer Compare Operation Enable Timer Clock Source 00 = internal (HSPCLK) 01 = external TCLKIN pin 10 = reserved 11 = QEP
6 5 4
TCLKS0

Period Register Select 0 = use own per. reg. 1 = use Timer 1 per. reg (bit reserved in T1CON)

3
TCLD1

2
TCLD0

T2SWT1 TENABLE TCLKS1

TECMPR SELT1PR

Start with Timer 1 0 = use own TENABLE 1 = use Timer 1 TENABLE (bit reserved in T1CON)

Compare Register Reload Condition 00 = when counter equals zero (underflow) 01 = when counter equals zero or period reg 10 = immediately 11 = reserved
5 - 12

5 - 10

DSP28 - Event Manager

GP Timer Registers

Now lets make a calculation. Assume that your task is to setup a PWM signal with a period of 50 kHz and a pulse width of 25%:

GP Timer Compare PWM Exercise

Symmetric PWM is to be generated as follows:
50 kHz carrier frequency Timer counter clocked by 30Mhz, PLL: multiply by 10/2, HSPCLK = divide by 2 Use the 1 prescale option 25% duty cycle initially Use GP Timer Compare 1 with PWM output active high T2PWM/T2CMP pins forced low Determine the initialization values needed in the GPTCONA, T1CON, T1PR, and T1CMPR registers
5 - 14

Solution :

PLLCR HSPCLK GPTCONA T1CON T1PR T1CMPR

= = = = = =

DSP28 - Event Manager

5 - 11

GP Timer Interrupts

GP Timer Interrupts
To enable one of the interrupt sources of Event Manager A we have to set a bit inside EVAIMRA, B or C.

EVAIMRA Register
@ 0x742C
12
-

15
-

14
-

13
-

11
-

10

8
T1CINT

T1OFINT T1UFINT

7
T1PINT

6
-

5
-

4
-

CMP3INT CMP2INT CMP1INT PDPINT

Interrupt Mask Bits 0 = disable interrupt 1 = enable interrupt

Bit 10: 9: 8: 7: 3: 2: 1: 0:

Event Timer 1 Overflow Timer 1 Underflow Timer 1 Compare match Timer 1 Period match Compare Unit 3, Compare match Compare Unit 2, Compare match Compare Unit 1, Compare match Power Drive Protect input, EVA

5 - 16

EVAIMRB Register
@ 0x742D
12
-

15
-

14
-

13
-

11
-

10
-

9
-

8
-

7
-

6
-

5
-

4
-

1
T2CINT

0
T2PINT

T2OFINT T2UFINT

Interrupt Mask Bits 0 = disable interrupt 1 = enable interrupt

Bit 3: 2: 1: 0:

Event Timer 2 Overflow Timer 2 Underflow Timer 2 Compare match Timer 2 Period match

5 - 17

5 - 12

DSP28 - Event Manager

GP Timer Interrupts

EVAIMRC Register
@ 0x742E
12
-

15
-

14
-

13
-

11
-

10
-

9
-

8
-

7
-

6
-

5
-

4
-

3
-

CAP3INT CAP2INT CAP1INT

Interrupt Mask Bits 0 = disable interrupt 1 = enable interrupt

Bit 2: 1: 0:

Event Capture Unit 3 input Capture Unit 2 input Capture Unit 1 input

5 - 18

An interrupt event will be marked by the DSP in Register EVAIFRA, B and C.

EVAIFRx Register
15 14
-

13
-

12
-

11
-

10

8
T1CINT

EVAIFRA @ 0x742F
Read: 0 = no event 1 = flag set

T1OFINT T1UFINT

7
T1PINT

6
-

5
-

4
-

CMP3INT CMP2INT CMP1INT PDPINT

15

14
-

13
-

12
-

11
-

10
-

9
-

8
-

EVAIFRB @ 0x7430
Write: 0 = no effect 1 = reset flag

7
-

6
-

5
-

4
-

1
T2CINT

0
T2PINT

T2OFINT T2UFINT

15

14
-

13
-

12
-

11
-

10
-

9
-

8
-

EVAIFRA @ 0x7431

7
-

6
-

5
-

4
-

3
-

CAP3INT CAP2INT CAP1INT

5 - 19

DSP28 - Event Manager

5 - 13

Lab 5: Lets play a tune!

Lab 5: Lets play a tune!

Objective
The Zwickau Adapter board has a small loudspeaker connected to output T1PWM (a small on-board amplifier is also necessary) - close Jumper JP3 of the adapter board. The task for this lab exercise is to play 8 basic notes of an octave. Optionally, you can improve this lab to play a real tune. To keep it simple we will generate all notes as simple square waves. Of course, for a real musician this would be an offence because a real note is a pure sine wave and harmonics. To generate a sine wave one would have to adjust the pulse width of the PWM signal to the instantaneous voltage of the sine. This scheme is a basic principle to generate sine waves with the help of a PWM output, but as I said, lets keep it simple. If youve additional time in your laboratory and youd like to hear pure notes, then try it later.

Lab 5: Lets play a tune ! Aim:

Exercise with Event Manager A General Purpose Timer 1 Use Lab 4 as a starting point. In Lab 4 we initialised Core Timer 0 to request an interrupt every 50 ms. We can use this ISR to load the next note to T1PWM. Timer1 output T1PWM is connected to a loudspeaker

Basic Tune Frequencies:

c1 d e f g a h c2 : 264 Hz : 297 Hz : 330 Hz : 352 Hz : 396 Hz : 440 Hz : 495 Hz : 528 Hz

5 - 20

The result of Lab4 is a good starting point for Lab5. Recall that we initialized the core timer 0 to request an interrupt service every 50 milliseconds. Now we can use this interrupt service routine to load the next note into the period and compare register of T1. A time of 50 milliseconds is a little bit too fast, but we have a 50ms variable CpuTimer0.InterruptCount. If we wait until the value of this variable is 10 we know that an interval of 500ms is over. After this period we can play the next note starting with c1 and go to c2 in an endless loop. Or, try to play the notes alternately as an ascending and descending sequence (or: recall a nursery rhyme).

5 - 14

DSP28 - Event Manager

Lab 5: Lets play a tune!

New Registers involved in Lab 5:

General Purpose Timer Control A Timer 1 Control Register Timer 1 Period Register Timer 1 Compare Register Timer 1 Counter Register EV- Manager A Interrupt Flag A EV- Manager A Interrupt Flag B EV-Manager A Interrupt Flag C EV- Manager A Interrupt Mask A EV- Manager A Interrupt Mask B EV- Manager A Interrupt Mask C Interrupt Flag Register Interrupt Enable Register : : : : : : : : : : : : : GPTCONA T1CON T1PR T1CMPR T1CNT EVAIFRA EVAIFRB EVAIFRC EVAIMRA EVAIMRB EVAIMRC IFR IER

5 - 21

Procedure Open Files, Create Project File

1. Create a new project, called Lab5.pjt in E:\C281x\Labs. 2. Open the file Lab4.c from E:\C281x\Labs\Lab4 and save it as Lab5.c in E:\C281x\Labs\Lab5. 3. Add the source code file to your project:

Lab5.c

4. From C:\tidcs\c28\dsp281x\v100\DSP281x_headers\source add:

DSP281x_GlobalVariableDefs.c

From C:\tidcs\c28\dsp281x\v100\DSP281x_common\cmd add:

F2812_EzDSP_RAM_lnk.cmd

From C:\tidcs\c28\dsp281x\v100\DSP281x_headers\cmd add:

F2812_Headers_nonBIOS.cmd

DSP28 - Event Manager

5 - 15

Lab 5: Lets play a tune!

From C:\ti\c2000\cgtoolslib add:

rts2800_ml.lib

From C:\tidcs\c28\dsp281x\v100\DSP281x_common\source add to project:

DSP281x_CpuTimers.c DSP281x_PieCtrl.c DSP281x_PieVect.c DSP281x_DefaultIsr.c

Project Build Options

5. Setup the search path to include the peripheral register header files. Click: Project Build Options

Select the Compiler tab. In the preprocessor Category, find the Include Search Path (-i) box and enter:

C:\tidcs\C28\dsp281x\v100\DSP281x_headers\include;..\include
6. Setup the stack size: Inside Build Options select the Linker tab and enter in the Stack Size (-stack) box:

400
Close the Build Options Menu by Clicking <OK>.

Build and Load

7. Click the Rebuild All button or perform: Project Build

and watch the tools run in the build window. If you get errors or warnings debug as necessary. So far we just generated a new project Lab5 with the old code from Lab4. If you run the code now you should see the Knight Rider of Lab4. Now we can start to modify our code in Lab5.c.

5 - 16

DSP28 - Event Manager

Lab 5: Lets play a tune!

Modify Source Code

8. Open Lab5.c to edit: double click on Lab5.c inside the project window. First we have to cancel the parts of the code that we do not need any longer. The definition of array LED [8] in function main is of no use for this lab cancel it. 9. Next we have to change the GPIO multiplex status; we need T1PWM as signal at the pin. Go into function Gpio_select() and modify the multiplex register setup. 10. Go into your local function InitSystem and enable the clock for Event Manager A. 11. Inside main, just before the line: CpuTimer0Regs.TCR.bit.TSS = 0; we have to initialize the Event Manager Timer 1 to produce a PWM signal. This involves the registers GPTCONA, T1CON, T1CMPR and T1PR. For register GPTCONA it is recommended to use the bit-member of this predefined union to set bit TCMPOE to 1 and bit field T1PIN to active low. For register T1CON set

The TMODE-field to counting up mode; Field TPS to divide by 128; Bit TENABLE to disable timer (we will enable it later) Field TCLKS to internal clock Field TCLD to reload on underflow and Bit TECMPR to enable compare operation

12. Last question is: how do we initialize T1PR? Well, obviously we need 8 different values for our 8 basic notes. So lets define a new integer array frequency [8] as a local variable in main! 13. How do we initialize array frequency [8]? We can initialize the array together with the definition inside main: int frequency [8] = {?,?,?,?,?,?,?,?}; A basic octave is a fixed series of 8 frequencies. AND: there is a relationship between the basic note c1 (264 Hz) and the next notes: 264 Hz (c1) 297Hz (d) = 9/8 * c1 330Hz (e) = 5/4 * c1 352Hz (f) = 4/3 * c1
DSP28 - Event Manager

396Hz (g) = 3/2 * c1 440Hz (a) = 5/3 * c1 495Hz (b) = 15/8 * c1 528 Hz (c2) = 2 * c1
5 - 17

Lab 5: Lets play a tune!

What is the relationship between these frequencies and T1PWM? Answer: We have to setup T1PR to generate a PWM period according to this list. The equation is: T1_PWM_Freq = 150MHz / (HISPCP * TPS * T1PR) For c1 = 264 Hz we get: T1PR = 150MHz / (2 * 128 * 264 Hz) = 2219. For d = 297 Hz we use: T1PR = 150MHz / (2 * 128 * 297 Hz) = 1973. Calculate the 8 initial numbers and complete the initial part for array frequency!

14. Next step: Modify the endless while(1) loop of main! Recall: i. The Core Timer T0 requests an interrupt every 50 milliseconds.

ii. The Watchdog Timer is alive! It will trigger a reset after 33ns*512*256*WDPS. If WDPS was initialized to 64 this reads as 280ms. iii. Timer T0 Interrupt Service Routine increment variable CpuTimer0.InterruptCount every 50 milliseconds We have to reset the watchdog every 200 milliseconds and we should play the next note after 500 milliseconds. Two tasks within this while(1) loop. Later we will learn that this type of multi tasking is much better solved with the help of DSP/BIOS Texas Instruments Real Time Operating System. For now we have to do it by our self. How can we find out, if a period of 200ms is over? We just have to test if CpuTimer0.InterruptCount is a multiple of 4. In language C this could be done by modulo division with 4 reminder is zero: if ((CpuTimer0.InterruptCount%4)==0) If it is TRUE then we have to perform the second half of the watchdog re-trigger sequence: EALLOW; SysCtrlRegs.WDKEY = 0xAA; EDIS; In a similar technique we can wait for 10 times 50 ms = 500 ms before we apply the next note into T1PR and T1CMPR. In Lab4 we did a reset of variable CpuTimer0.InterruptCount every time a period was over. Doing so, we limited the values for this variable between 0 and 3, which was fine for this single task exercise. When we have to take care of more activities with different periods, it is not a good recommendation to reset this variable. A better approach is to build a time interval out of two read operations of CpuTimer0.InterruptCount. With the first access we gather the actual time and store this value in a local unsigned long variable
5 - 18 DSP28 - Event Manager

Lab 5: Lets play a tune!

time_stamp. With a second access to CpuTimer0.InterruptCount we can read the new time information and the difference between this value and the value of time_stamp is the elapsed time in multiples of 50ms. A wait instruction for 500ms could now look like this: if ( (CpuTimer0.InterruptCount time_stamp ) > 10) If TRUE, then:
Load time_stamp with CpuTimer0.InterruptCount Load the next note into EvaRegs.T1PR Load EvaRegs.T1CMPR = EvaRegs.T1PR/2 Enable T1PWM, set EvaRegs.T1CON.bit.TENABLE = 1 Implement and handle a status counter (variable i) to loop through array

frequency[8]

Build and Load

15. Click the Rebuild All button or perform: Project Build

and watch the tools run in the build window. If you get errors or warnings debug as necessary. 16. Load the output file down to the DSP Click: File Load Program and choose the desired output file.

Test
17. Reset the DSP by clicking on: Debug Debug Reset CPU Restart followed by

18. Run the program until the first line of your C-code by clicking: Debug Go main.

19. Debug your code as youve done in previous labs.

DSP28 - Event Manager

5 - 19

Event Manager Compare Units

Event Manager Compare Units

Compare Units (EVA)

Reset PIE

EV Control Registers / Logic GP Timer 1 Compare GP Timer 1 Data Bus Compare Unit 1 Compare Unit 2 Compare Unit 3 GP Timer 2 Compare GP Timer 2 MUX Capture Units

TCLKINA / TDIRA ADC Start T1PWM_T1CMP

Output Logic

PWM Circuits Output Logic PWM Circuits Output Logic PWM Circuits Output Logic Output Logic
CLK DIR

PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 T2PWM_T2CMP

QEP Circuit
CAP1/QEP1 CAP2/QEP2 CAP3/QEPI1
5 - 22

A compare unit is a peripheral that is designed to generate pulse width modulated (PWM) output signals. What is a PWM signal and what is it used for?

What is Pulse Width Modulation?

PWM is a scheme to represent a signal as a sequence of pulses
fixed carrier frequency fixed pulse amplitude pulse width proportional to instantaneous signal amplitude PWM energy original signal energy

Differs from PAM (Pulse Amplitude Modulation)

fixed width, variable amplitude
5 - 23

5 - 20

DSP28 - Event Manager

Event Manager Compare Units

With a PWM signal we can represent any analogue output signal as a series of digital pulses! All we need to do with this pulse series is to integrate it (with a simple low pass filter) to imitate the desired signal. This way we can build a sine wave shaped output signal. The more pulses we use for one period of the desired signal, the more precisely we can imitate it. We speak very often of two different frequencies, the PWM-frequency (or sometimes carrier frequency) and the desired signal frequency.

PWM Signal Representation

Original Signal

same areas (energy)

PWM representation

PAM representation
5 - 24

A lot of practical applications have an internal integrator, for example the windings of an electrical motor are perfectly suited to behave as a low-pass filter. One of the most used applications of PWM is digital motor control. Why is that? Answer: The overall goal is to control electrical drives by imprinting harmonic voltages and currents into the windings of the motor. This is done to avoid electromagnetic distortions of the environment and to achieve a high power factor. To induce a sine wave shaped signal into the windings of a motor we would have to use an amplifier to achieve high currents. The simplest amplifier is a standard NPN or PNP transistor that proportionally amplifies the base current into the collector current. Problem is, for high currents we cant force the transistor into its linear area; this would generate a lot of thermal losses and for sure exceed its maximal power dissipation. The solution is to use this transistor in its static switch states only (On: Ice = Icesat, Off: Ice = 0). In this states a transistor has its smallest power dissipation. AND: by adapting the switch pattern of a PWM (recall: amplitude is 1 or 0 only) we can induce a sine wave shaped current!

DSP28 - Event Manager

5 - 21

Event Manager Compare Units

Why Use PWM in Digital Motor Control?

Desired motor phase currents or voltages are known Power switching devices are transistors
Difficult to control in proportional region Easy to control in saturated region

PWM is a digital signal easy for DSP to output

DC Supply DC Supply

Desired signal to motor phase

PWM

PWM approx. of desired signal

Unknown Gate Signal

Gate Signal Known with PWM

5 - 25

We have two different options to generate a PWM-signal, asymmetric and symmetric PWM.

Asymmetric PWM Waveform

TPWM

Period Compare

Counter

Tpwm / Tcmp Pin (active high)

Caused by Period match (toggle output in Asym mode only) Caused by Compare match

5 - 26

5 - 22

DSP28 - Event Manager

Event Manager Compare Units

Symmetric PWM Waveform

TPWM

Period Compare Counter

TPWM /TCMP Pin (active high) Interrupts General Purpose Timer Full Compare Units TPWM/TCMP Pin

Period Compare Counter

Compare Compare Compare

PWM1 PWM2 PWM3 PWM4 PWM5 PWM6

5 - 27

NOTE: The value in T1PR defines the length of a period TPWM in asymmetric operating mode. For symmetric mode the value of TxPR defines only half of the length of a period TPWM. The Compare Unit consists of 6 output signals PWM1 to PWM6. The time base is derived from Event Manager Timer1, e.g. register T1PR together with the setup for T1 (Register T1CON) defines the length of a PWM-period for all six output signals. Register T1CNT is used as the common counter register. With 3 new registers CMPR1,CMPR2and CMPR3 we can specify 3 different switch pattern based on T1PR. Obviously this leads to a 3-phase control pattern for 3 phase electrical motors. Each Compare Unit is able to drive a pair of two output signals. With the help of its own output logic we usually define the two lines to be opposite or 180-degree out of phase to each other - a typical pattern for digital motor control. The next slide shows a typical layout for a three-phase power-switching application.

DSP28 - Event Manager

5 - 23

Event Manager Compare Units

Voltage source inverter components

Upper & lower devices can not be turned on simultaneously (dead band)

PWM signal is applied between gate and source

DC bus capacitor

Three phase outputs which go to the motor terminals

Power Switching Devices

5 - 28

Compare Units Block Diagram

Compare Units Block Diagram (EVA)

ACTRA . 11 - 0 T1CNT . 15 - 0 Shadowed

GP Timer 1 Counter
DBTCONA . 11 - 2

Compare Action Control Register Dead Band Units Output Logic

COMCONA . 9 FCOMPOE

Compare Logic Compare Register

Shadowed CMPRx . 15 - 0

PWMy, y+1

Note: x = 1, 2, 3; y = 1, 3, 5

5 - 29

5 - 24

DSP28 - Event Manager

Event Manager Compare Units

The central block of the Compare Unit is a compare logic that compares the value of Event Manager Timer 1 counter register T1CNT against Compare Register CMPRx. If there is a first match, a rising edge signal goes into the next block called Dead Band Unit. With the second match between T1CNT and CMPRx in symmetric PWM mode a falling edge signal is generated. We will discuss this Dead Band Unit a little bit later. We do have three Compare Units available. The output logic is controlled by means of a register, called Action Control Register ACTRA and register COMCONA. With the help of this register set we can adjust the shape of the physical PWM output signal to our needs. We can specify four types for all 6 output lines:

Active High: o First CMPRx match switches PWM output from 0 to 1. After second CMPRx match the signal is set back to 0.

Active Low: o First CMPRx match switches PWM output from 1 to 0. After second CMPRx match the signal is setback to 1.

Forced High: o PWM output always at 0.

Forced Low: o PWM output always at 1.

Compare Unit Registers

Register
ACTRA

Address

Description

COMCONA 0x007411 Compare Control Register A 0x007413 Compare Action Control Register A 0x007417 Compare Register 1 0x007418 Compare Register 2 0x007419 Compare Register 3 0x007513 Compare Action Control Register B 0x007515 Dead-Band Timer Control Register B 0x007517 Compare Register 4 0x007518 Compare Register 5 0x007519 Compare Register 6 DBTCONA 0x007415 Dead-Band Timer Control Register A CMPR1 CMPR2 CMPR3 ACTRB

EVA

COMCONB 0x007511 Compare Control Register B DBTCONB CMPR4 CMPR5 CMPR6

EVB

EXTCONA 0x007409 / EXTCONB 0x007509 ;Extension Control Register

5 - 30

DSP28 - Event Manager

5 - 25

Event Manager Compare Units

The next two slides explain the set up for the individual bit fields of COMCONA. Most of the bits are reserved in basic operation mode (EXTCONA [0] = 0).

Compare Control Register (EVA)

Upper Byte:
Compare Enable
0 = disable 1 = enable

COMCONA @ 0x007411

Space Vector PWM 0 = SV disable 1 = SV enable

Full Compare Output Enable

(reserved when EXTCONA[0]=1) 0 = all disable (hi-impedance) (hi1 = all enable
11 10 9 8

15
CENABLE

14
CLD1

13
CLD0

12

SVENABLE ACTRLD1 ACTRLD0 FCOMPOE PDPINTA

CMPRx reload condition

00 = when T1CNT = 0 01 = when T1CNT = 0 or T1PR 10 = immediately 11 = reserved

ACTRA reload condition

00 = when T1CNT = 0 01 = when T1CNT = 0 or T1PR 10 = immediately 11 = reserved

PDPINT Status
0 = low 1 = high

5 - 31

Compare Control Register (EVA)

Lower Byte:
Full Compare 2 Output Enable (if EXTCONA[0]=1) 0 = disable 1 = enable
7 6 5 4
reserved

COMCONA @ 0x007411

FCMP2OE

Full Compare 2 Trip Enable (if EXTCONA[0]=1) 0 = disable 1 = enable

3
reserved

C2TRIPE

RESERVED RESERVED RESERVED

RESERVED RESERVED RESERVED

Full Compare 3 Output Enable

(if EXTCONA[0]=1) (if EXTCONA[0]=1) (if EXTCONA[0]=1) 0 = disable 0 = disable 0 = disable 1 = enable 1 = enable 1 = enable

FCMP3OE

Full Compare 1 Output Enable

FCMP1OE

Full Compare 3 Trip Enable

C3TRIPE

Full Compare 1 Trip Enable (if EXTCONA[0]=1) 0 = disable 1 = enable

5 - 32

C1TRIPE

5 - 26

DSP28 - Event Manager

Event Manager Compare Units

COMCONA [15] is the enable bit for the three phase compare units. With COMCONA [14:13] and COMCONA [11:10] we specify the point in time when the compare registers and action control registers are reloaded (shadow register content into foreground). As we have seen with the timers we can prepare the next period in the current running period. COMCONA [8] shows the status of the power drive protection flag. If it is a 1, the DSP has seen an interrupt request from its over-current input PDPINT. With EXTCONA [0] =1 all three pairs of compare output lines can be enabled independently of each other. If EXTCONA [0] =0 then all six lines are enabled with COMCONA [9] =1. If EXTCONA [0] =1 we can use three more individual over current inputs signals. To use these over current signals we can enable or disable this feature using bits COMCONA [2:0]. COMCONA [12] = 1 enables a special switch pattern for digital motor control, called Space Vector Modulation (SVM). This feature is built-in hardware support for one specific theoretical control algorithm. For details see literature or your lectures about power electronics.

Extension Control Register A (EVA)

EXTCONA @ 0x007409 Independent Compare Output Enable Mode
0 = disable 1 = enable

QEP Index Enable

0 = disable 1 = enable

15-4 reserved

3 EVSOCE

2 QEPIE

1 QEPIQUAL

0 INDCOE

EV Start-of-Conversion Output Enable

0 = disable 1 = enable

CAP3/QEPI Index Qualification Mode

0 = off 1 = on

5 - 33

DSP28 - Event Manager

5 - 27

Event Manager Compare Units

Compare Action Control Register (EVA)

ACTRA @ 0x007413
Basic Space Vector Bits
can write as 0 when SV not in use 15
SVRDIR

14
D2

13
D1

12
D0

11

10

CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0

CMP4ACT1 CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0 CMP1ACT1 CMP1ACT0

Pin Action on Compare: CMPyACT1-0 00 01 10 11 force low active low active high forced high
5 - 34

SV Rotation Direction
can write as 0 when SV not in use

ACTRA [11:0] define the shapes of the six PWM output signals as discussed before. ACTRA [15:12] are used to support Space Vector Modulation. Bit 15 defines the rotation direction of the resulting electromagnetic vector as clockwise or anti clockwise. ACTRA [14:12] declare the Basic Space Vector for the next PWM periods. A Basic Space Vector is a 60-degree section of the unit circle. This gives 6 vectors per rotation plus two virtual vectors with no current imprint. If SVM is not used, one can initialize bits 15:12 to zero.

5 - 28

DSP28 - Event Manager

Event Manager Compare Units

Hardware Dead Band Unit

Dead-band control provides a convenient means of combating current shoot-through problems in a power converter. Shoot-through occurs when both the upper and lower transistors in the same phase of a power converter are on simultaneously. This condition shorts the power supply and results in a large current draw. Shoot-through problems occur because transistors (especially FETs) turn on faster than they turn off, and also because high-side and low-side power converter transistors are typically switched in a complimentary fashion. Although the duration of the shootthrough current path is finite during PWM cycling, (i.e. the transistor will eventually turn off), even brief periods of a short circuit condition can produce excessive heating and stress the power converter and power supply.

Motivation for Dead-Band

supply rail Gate Signals are Complementary PWM

to motor phase

Transistor gates turn on faster than they shut off Short circuit if both gates are on at same time!
5 - 35

Two basic approaches exist for controlling shoot-through: modify the transistors, or modify the PWM gate signals controlling the transistors. In the first case, the switch-on time of the transistor gate must be increased so that it (slightly) exceeds the switch-off time. The hard way to accomplish this is by adding a cluster of passive components such as resistors and diodes in series with the transistor gate to act as low-pass filter to implement the delay. The second approach to shoot-through control separates transitions on complimentary PWM signals with a fixed period of time. This is called dead-band. While it is possible to perform software implementation of dead-band, the C28x offers on-chip hardware for this purpose that requires no additional CPU overhead. Compared to the passive approach, dead-band offers more precise control of gate timing requirements.

DSP28 - Event Manager

5 - 29

Event Manager Compare Units

Dead-Band Functionality (EVA)

Clock PHx DT DTPHx DTPHx_ dead time DT 4-bit period
DBTCONA . 11 - 8

HSPCLK

Prescaler
DBTCONA . 4 - 2

PHx

edge detect

ENA

reset

4-bit Counter

comparator

Asymmetric PWM Example

DTPHx DTPHx_
5 - 36

Each compare unit has a dead-band timer, but shares the clock prescaler unit and the dead-band period with the other compare units. Dead-band can be individually enabled for each unit.

Dead-Band Timer Control Register (EVA)

DBTCONA @ 0x007415

dead time = DB period * DB prescaler * CPUCLK period

DB Timer Period
15 14 13 12 11 DBT3 5 EDBT1 4 10 DBT2 3 9 DBT1 2 8 DBT0 1 0

reserved reserved reserved reserved 7 EDBT3 6 EDBT2

DBTPS2 DBTPS1 DBTPS0 reserved reserved

DB Timer Enable
0 = disable 1 = enable

DB Timer Prescaler
000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 32 111 = 32
5 - 37

5 - 30

DSP28 - Event Manager

Capture Units

Capture Units

Capture Units (EVA)

Reset PIE

EV Control Registers / Logic GP Timer 1 Compare GP Timer 1 Data Bus Compare Unit 1 Compare Unit 2 Compare Unit 3 GP Timer 2 Compare GP Timer 2 MUX Capture Units

TCLKINA / TDIRA ADC Start T1PWM_T1CMP

Output Logic

PWM Circuits Output Logic PWM Circuits Output Logic PWM Circuits Output Logic Output Logic
CLK DIR

PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 T2PWM_T2CMP

QEP Circuit
CAP1/QEP1 CAP2/QEP2 CAP3/QEPI1
5 - 38

The capture units allow time-based logging of external logic level signal transitions on the capture input pins. Event Manager A has three capture units, and each is associated with a capture input pin. The time base is selectable to be either GP timer 1 or 2. The timer value is captured and stored in the corresponding 2-level-deep FIFO stack when a specified transition is detected on a capture input pin. Capture Unit 3 can be configured to trigger an A/D conversion that is synchronized with an external signal of a capture event.

DSP28 - Event Manager

5 - 31

Capture Units

Capture Units

Timer
Trigger

Timestamp Values

Capture units timestamp transitions on capture input pins Three capture units (per event manager) each associated with a capture input pin
5 - 39

Three potential uses for the Capture Units are: Measurement of the width of a pulse or a digital signal Automatic start of the AD Converter by a Capture Event from CAP3 Low speed estimation of a rotating shaft. A potential advantage for low speed estimation is given when we use time capture (16Bit resolution) instead of position pulse counting (poor resolution in slow mode).

5 - 32

DSP28 - Event Manager

Capture Units

Some Uses for the Capture Units

Synchronized ADC start with capture event Measure the time width of a pulse Low speed velocity estimation from incr. encoder:
Problem: At low speeds, calculation of x -x vk k k-1 speed based on a measured position t change at fixed time intervals produces large estimate errors Alternative: Estimate the speed using a measured time interval at fixed position intervals vk x tk - tk-1
Signal from one Quadrature Encoder Channel

x
5 - 40

Capture Units Block Diagram

The edge detector stores the current value of the time base counter into a FIFO-buffer.

Capture Units Block Diagram (EVA)

T1CNT . 15 - 0 T2CNT . 15 - 0

GP Timer 1 Counter

GP Timer 2 Counter
CAPCONA . 14 -12

Can latch on:

rising edge falling edge both
CAP3TOADC CAPCONA . 8

CAPCONA . 10 - 9

MUX

Enable

Edge Detect / 2-Level Deep FIFO

CAPxFIFO Status CAPFIFOA . 13 - 8 RS Edge Select CAPCONA . 7 - 2

ADC Start (CAP 3) CAP1,2,3

CAPRESET CAPCONA . 15

TTL Signal min. valid width: 2 CPUCLK lo 2 CPUCLK hi

5 - 41

DSP28 - Event Manager

5 - 33

Capture Units

Capture Units Registers

Capture Units Registers

Register
CAPCONA CAPFIFOA CAP1FIFO CAP2FIFO CAP3FIFO CAP1FBOT CAP2FBOT CAP3FBOT CAPCONB CAPFIFOB CAP4FIFO CAP5FIFO CAP6FIFO CAP4FBOT CAP5FBOT CAP6FBOT

Address
0x007420 0x007422 0x007423 0x007424 0x007425 0x007427 0x007428 0x007429 0x007520 0x007522 0x007523 0x007524 0x007525 0x007527 0x007528 0x007529

Description
Capture Control Register A Capture FIFO Status Register A Two-Level Deep FIFO 1 Stack Two-Level Deep FIFO 2 Stack Two-Level Deep FIFO 3 Stack Bottom Register of FIFO 1 Bottom Register of FIFO 2 Bottom Register of FIFO 3 Capture Control Register B Capture FIFO Status Register B Two-Level Deep FIFO 4 Stack Two-Level Deep FIFO 5 Stack Two-Level Deep FIFO 6 Stack Bottom Register of FIFO 4 Bottom Register of FIFO 5 Bottom Register of FIFO 6
5 - 42

EVA

EVB

EXTCONA 0x007409 / EXTCONB 0x007509 ;Ext. Cntrl Reg.

Capture Control Register (EVA)

CAPCONA @ 0x007420
Unit 3 Control
0 = disable 1 = enable 12
CAP3EN

Capture Reset (not latched)

0 = clear all result FIFOs and CAPFIFO register 1 = no action 15
CAPRES

ADC Start
0 = no action 1 = CAP3INT flag 11 10 9 8

14-13
CAPQEPN

reserved

CAP3TSEL CAP12TSEL CAP3TOADC

Unit 1 & 2 Control

00 = disable 01 = enable for capture 10 = reserved 11 = enable for QEP 7-6 CAP1EDGE 5-4 CAP2EDGE 3-2

Timer Select
0 = GP Timer 2 1 = GP Timer 1 1-0 reserved

CAP3EDGE

Edge Detection Control

00 = no detection 01 = rising edge 10 = falling edge 11 = both edges
5 - 43

5 - 34

DSP28 - Event Manager

Capture Units

CAPCONA [15] is a reset bit for the Capture state machine and the status of the FIFO. It should be used in a single instruction to reset the Capture units during initialization. Note: to execute reset you will have to apply a zero! With CAPCONA [14-12] the Capture Units are enabled. Please note that CAP1 and CAP2 are enabled jointly, whereas CAP3 has its own enable bit. CAPCONA [10-9] are used to select the clock base for the capture units. Again, for CAP1 and CAP2 we have to select the same GP timer. CAPCONA [8] allows CAP3 to start an AD conversion. Of course, before we use this option, we have to initialize the ADC. This will be explained in the next chapter. CAPCONA [7-2] specify if the capture units are triggered with a rising or falling edge or with both edges.

Capture FIFO Status Register (EVA)

CAPFIFOA @ 0x007422

15-14 reserved

13-12

11-10

9-8

7-0 reserved

CAP3FIFO

CAP2FIFO

CAP1FIFO

CAPxFIFO bits are automatically adjusted on a capture or FIFO read

FIFOx Status:
00 = empty 01 = one entry 10 = two entries 11 = three entries attempted, 1st entry lost

5 - 44

Register CAPFIFOA reflects the filling status of the three result register FIFOs. In case of an overflow the oldest entry will be lost. This principle ensures that a capture unit stores the two latest measurement results. If our program performs a read access to one of the FIFO result registers the status value in the corresponding CAPFIFOA bit field is decremented.

DSP28 - Event Manager

5 - 35

Quadrature Encoder Pulse Unit (QEP)

Quadrature Encoder Pulse Unit (QEP)

What is an Incremental Quadrature Encoder?

A digital (angular) position sensor
photo sensors spaced /4 deg. apart slots spaced deg. apart light source (LED) Ch. A shaft rotation Incremental Optical Encoder Ch. B Quadrature Output from Photo Sensors /4

5 - 45

A QEP unit is normally used to derive direction and speed information from an incremental encoder circuit mounted on a rotating shaft. As shown on the previous slide two sensor signals are used to generate two digital pulse streams Channel A and Channel B.

Quadrature Encoder Pulse (EVA)

Reset PIE

EV Control Registers / Logic GP Timer 1 Compare GP Timer 1 Data Bus Compare Unit 1 Compare Unit 2 Compare Unit 3 GP Timer 2 Compare GP Timer 2 MUX Capture Units

TCLKINA / TDIRA ADC Start T1PWM_T1CMP

Output Logic

PWM Circuits Output Logic PWM Circuits Output Logic PWM Circuits Output Logic Output Logic
CLK DIR

PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 T2PWM_T2CMP

QEP Circuit
CAP1/QEP1 CAP2/QEP2 CAP3/QEPI1
5 - 46

5 - 36

DSP28 - Event Manager

Quadrature Encoder Pulse Unit (QEP)

The time relationship between A and B lead to a state machine with four states. Depending on the sequence of states and the speed of alternation, the QEP unit timer is decremented or incremented. By reading and comparing this timer counter information at fixed intervals, we can obtain speed and/or position information.

How is Position Determined from Quadrature Signals?

Position resolution is /4 degrees.
(A,B) = (00) (11) (10) (01)

increment counter

10

decrement counter

Ch. A Ch. B

Quadrature Decoder 00 11 State Machine 01

5 - 47

Incremental Encoder Connections (EVA)

Ch. A

QEP decoder logic

CLK DIR

.
QEPIQUAL

CAP1/QEP1 CAP2/QEP2

Ch. B

Index
CAP3/QEPI

GP Timer 2 selected as pulse counter Timer Prescaler bypassed (i.e. Prescale always 1)

QEPIE

GP Timer 2

5 - 48

DSP28 - Event Manager

5 - 37

Quadrature Encoder Pulse Unit (QEP)

Extension Control Register A (EVA)

EXTCONA @ 0x007409 Independent Compare Output Enable Mode
0 = disable 1 = enable

QEP Index Enable

0 = disable 1 = enable

15-4 reserved

3 EVSOCE

2 QEPIE

1 QEPIQUAL

0 INDCOE

EV Start-of-Conversion Output Enable

0 = disable 1 = enable

CAP3/QEPI Index Qualification Mode

0 = off 1 = on

5 - 49

The third capture input pin QEPI1can be used as an absolute position information signal for a zero degree crankshaft position. This signal is then used to reset the QEP timer to its initial state. To enable the QEPI1 index function we have set EXTCONA [2] to 1. Then we have two more options, selected with EXTCONA [1]: Use index pulse QEPI1 independent from the state of QEP1 and QEP2 Use index pulse QEPI1 as a valid trigger pulse only if this event is qualified by the state of QEP1 = 1 AND QEP2 = 1.

5 - 38

DSP28 - Event Manager

Lab 5A: Generate a PWM sine wave

Lab 5A: Generate a PWM sine wave

Objective
So far we generated square wave signals to drive a loudspeaker. To ask a musician to listen to this type of music would be impudent. So lets try to improve the shape of our output signals. A musical note is a pure - or harmonic sine wave signal of a fixed frequency. The objective of this lab exercise is to generate a harmonic sine wave signal out of a series of pulse width modulated digital pulses (PWM). Remark: The first generation of cell phones used the square wave technology to generate ringing sounds. Compare this with todays latest cell phones!

Procedure Open Files, Create Project File

1. Create a new project, called Lab5A.pjt in E:\C281x\Labs. 2. Open the file Lab5.c from E:\C281x\Labs\Lab5 and save it as Lab5A.c in E:\C281x\Labs\Lab5A. 3. Add the source code file to your project:

Lab5A.c

4. From C:\tidcs\c28\dsp281x\v100\DSP281x_headers\source add:

DSP281x_GlobalVariableDefs.c

From C:\tidcs\c28\dsp281x\v100\DSP281x_common\cmd add:

F2812_EzDSP_RAM_lnk.cmd

From C:\tidcs\c28\dsp281x\v100\DSP281x_headers\cmd add:

F2812_Headers_nonBIOS.cmd

From C:\tidcs\c28\dsp281x\v100\DSP281x_common\source add to project:

DSP281x_PieCtrl.c DSP281x_PieVect.c DSP281x_DefaultIsr.c

From C:\ti\c2000\cgtoolslib add:

DSP28 - Event Manager 5 - 39

Lab 5A: Generate a PWM sine wave

rts2800_ml.lib

Project Build Options

5. Setup the search path to include the peripheral register header files. Click: Project Build Options

Select the Compiler tab. In the preprocessor Category, find the Include Search Path (-i) box and enter:

C:\tidcs\C28\dsp281x\v100\DSP281x_headers\include; ..\include; C:\tidcs\C28\IQmath\cIQmath\include

6. Setup the stack size: Inside Build Options select the Linker tab and enter in the Stack Size (-stack) box:

400
Close the Build Options Menu by Clicking <OK>.

Modify Source Code

7. Open Lab5A.c to edit: double click on Lab5A.c inside the project window. First we have to cancel the parts of the code that we do not need any longer. We will not use the CPU core timer 0 in this exercise; therefore we do not need the prototype of interrupt service routine cpu_timer0_isr(). Instead, we need a new ISR for GP Timer1-Compare-Interrupt. Add a new prototype interrupt function: interrupt void T1_Compare_isr(void). 8. We do not need the variables i,time_stamp and frequency[8] from Lab5 - delete their definition lines at the beginning of function main. 9. Next, modify the re-map lines for the PIE entry. Instead of PieVectTable.TINT0 = & cpu_timer0_isr we need to re-map: PieVectTable.T1CINT = &T1_Compare_isr; 10. Delete the next two function calls: InitCpuTimers(); and ConfigCpuTimer(&CpuTimer0, 150, 50000); and add an instruction to enable the EVA GP Timer1 Compare interrupt. Recall Module 4 Interrupt System and verify that the EVA GP Timer1 Compare interrupt is connected to PIE Group2 Interrupt 5. Which Register do we have to initialize? Answer: PieCtrlRegs.PIEIER2.bit.INTx5 = 1; Also modify the set up for register IER into: IER = 2;

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Lab 5A: Generate a PWM sine wave

11. Next we have to initialize the Event Manager Timer 1 to produce a PWM signal. This involves the registers GPTCONA, T1CON, T1CMPR and T1PR. For register GPTCONA it is recommended to use the bit-member of this predefined union to set bit TCMPOE to 1 and bit field T1PIN to active low. For register T1CON set

The TMODE-field to counting up mode; Field TPS to divide by 1; Bit TENABLE to disable timer; Field TCLKS to internal clock Field TCLD to reload on underflow Bit TECMPR to enable compare operation

12. Remove the 3 lines before the while(1)-loop in main:

CpuTimer0Regs.TCR.bit.TSS = 0; i = 0; time_stamp = 0;

and add 4 new lines to initialise T1PR, T1CMPR, to enable GP Timer1 Compare interrupt and to start GP Timer 1: EvaRegs.T1PR = 1500; EvaRegs.T1CMPR = EvaRegs.T1PR/2; EvaRegs.EVAIMRA.bit.T1CINT = 1; EvaRegs.T1CON.bit.TENABLE = 1;

What is this number 1500 for? Well, it defines the length of a PWM period:

f PWM =

f CPU T 1PR TPST 1 HISCP

with TPST1=1, HISCP = 2, fCPU = 150MHz and a desired fPWM = 50kHz we derive: T1PR = 1500! T1CMPR is preloaded with half of T1PR. Whys that? Well, in general T1CMPR defines the width of the PWM-pulse. Our start-up value obviously defines a pulse width of 50%.

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Lab 5A: Generate a PWM sine wave

Recall slide 5-24: PWM-Representation

PWM Signal Representation

Original Signal

same areas (energy)

PWM representation

PAM representation
5 - 24

A duty cycle of 50% represents a sine angle of 0 degrees! And, it makes sense to initialize the PWM unit for this angle. From the bottom left of the slide we can derive: Degree 0 90 180 270 360 Sin 0 1 0 -1 0 Duty Cycle 50% 100% 50% 0% 50%

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Lab 5A: Generate a PWM sine wave

13. Modify the endless while(1) loop of main! We will perform all activities using GP Timer 1 Compare Interrupt Service. Therefore we can delete almost all lines of this main background loop, we only have to keep the watchdog service: while(1) { EALLOW; SysCtrlRegs.WDKEY = 0xAA; EDIS; } 14. Rename the interrupt service routine cpu_timer0_isr into T1_Compare_isr. Remove the line CpuTimer0.InterruptCount++; and replace the last line of this routine by: PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; Before this line add another one to acknowledge the GP Timer 1 Compare Interrupt Service is done. Remember how? The Event Manager has 3 interrupt flag registers EVAIFRA,EVAIFRB and EVAIFRC. We have to clear the T1CINT bit (done by setting of the bit): EvaRegs.EVAIFRA.bit.T1CINT = 1;

Build and Load

15. Click the Rebuild All button or perform: Project Build

and watch the tools run in the build window. If you get syntax errors or warnings debug as necessary. 16. Load the output file down to the DSP Click: File Load Program and choose the desired output file.

Test
17. Reset the DSP by clicking on: Debug Debug Debug Reset CPU Restart Go main. followed by and

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Lab 5A: Generate a PWM sine wave

18. When you now run the code the DSP should generate a 50 kHz PWM signal with a duty cycle of 50% on T1PWM. If you have an oscilloscope you can use jumper JP7 (in front of the loudspeaker) of the Zwickau Adapter board to measure the signal. If your laboratory cant provide a scope, you can set a breakpoint into the interrupt service routine of T1 Compare at line PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; Verify that your breakpoint is hit periodically, that register T1PR holds 1500 and register T1CMPR is initialized with 750. Use the watch window to do so. Do not continue with the next steps until this point is reached successfully! Instead go back and try to find out, what went wrong during the modification of your source code.

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Lab 5A: Generate a PWM sine wave

Generate the sine wave

So far we generated a pure square wave PWM signal of 50 KHz. Our goal is to produce a sine wave signal which is build up from a series of this 50 KHz carrier period cycles. We have to modify the pulse width according to the current sine angle. Obviously we have to increment the angle from 0 to 360 in a couple of steps.

Question is: how do we calculate the sine-values? Use the sin(x) function
This function is part of the C compilers math.lib. All we would need to do is to add the header file math.h to our project. Problem: sin(x) is a floatingpoint function; our DSP is a fixed point processor. That means the compiler has to generate quite a lot of assembler instructions to calculate the sine values. This will cost us a quite a lot of CPU time, just to calculate the same series of sine values over and over. Feasible, but not recommended

Use a lookup table with pre calculated sine values

We do not need a floating-point precision; our goal is to adjust the 16-bit register T1CMPR. It is much quicker to prepare an array with precalculated sine values. Instead of calculating the next value during runtime we access a table with pre-defined results of sine calculations. This principle is called Lookup Table Access and is widely used in embedded control. Almost all control units for automotive electronics are using one or more of these lookup tables, not only for trigonometric functions but also for control parameters. Highly recommended

Next Question:
How do we generate a lookup table? Well, use a calculator, note all results and type them into an array! How many values? Well, the more values we have the better we can approximate the analogue sine wave shape! Recall, we need sine values from 0 to 360. Sounds like a lot of boring work, doesnt it? Answer: Texas Instruments has already done the work for you. The C28x DSP comes with a BOOT-ROM (see memory map module 1). A part of this memory area is a sine wave table! From Address 0x3F F000 to 0x3F F3FF we find 512 values for sin(x). The numbers are stored as 32 Bit numbers in Q30-notation. With 512 entries we have an angle step of 0.703 (360/512) for a unit circle.

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Lab 5A: Generate a PWM sine wave

But what is Q30?

Q30 or I2Q30 is a fractional fixed-point representation of 32-Bit numbers. We will discuss the advantage of fractional numbers for embedded control in detail in Part 2 of this DSP course. So far, lets try to understand the basics: The data format Q30 separates a 32-bit number into an integer part and a fractional part. The integer part is the usual sequence of positive powers of 2; the fractional part is the sequence of negative powers of 2. For a Q30 number we get the following binary representation:

Bit 31 (-1)*21

Bit 30 1*20

Bit 29 1*2-1

Bit 28 1*2-2

Bit 27 1*2-3

Bit 26 1*2-4

Bit 25 1*2-5

The decimal range of a Q30 number is 2...+1.9999: Most negative number: Decimal minus 1: Smallest negative number Zero Smallest positive number Decimal plus 1: Most positive number: 0x8000 0000 0xC000 0000 0xFFFF FFFF 0x0000 0000 0x0000 0001 0x4000 0000 0x7FFF FFFF: -2 -1 -9.31322e-10 0 +9.31322e-10 +1 +1.999999999

IQ-Math Library
Texas Instruments has built a whole library of fixed-point math operations based on this Q-format. This library called IQ-Math is widely used in closed control applications like digital motor control, FAST FOURIER TRANSFORM (FFT) or digital filters (FIR, IIR). The library is free, no royalties and can be downloaded from TIs web. The appendix of this CD contains the current version of IQ-Math. We will discuss and use this library in a specific module in Part 2 of this DSP course.

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Lab 5A: Generate a PWM sine wave

Boot ROM Table

The following table shows the contents of the sine wave area of the Boot ROM:

Address 0x3F F000 0x3F F002 0x3F F004 0x3F F006 ... 0x3F F100 .... 0x3F F200 .... 0x3F F300 .... 0x3F F3FE

Low word 0x0000 0x0E90 0x155F 0x0CAF

High Word 0x0000 0x00C9 0x0192 0x025B

Angle in 0 0.703 1.406 2.109

Sine value in IQ30 0.0 0.01227153838 0.02454122808 0.03680722322

0x0000

0x4000

90

1.0

0x0000

0x0000

180

0.0

0x0000

0xC000

270

-1.0

0xF170

0xFF36

359,3

-0.01227153838

Resume Lab Exercise 5A

Lets resume the procedure for Lab5A: 19. How do we get access to this boot ROM sine wave table? We have to add some basic support from the IQ-Math library to our project. At the top of your code, just after the line #include DSP281x_Device.h add the next lines: #include IQmathLib.h #pragma DATA_SECTION(sine_table, IQmathTables); _iq30 sine_table[512];

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Lab 5A: Generate a PWM sine wave

The #pragma statement declares a specific data memory area, called IQmathTables. This area will be linked in the next procedure step to the address range of the Boot ROM sine table. The global variable sine_table[512] is an array of this new data type IQ30. 20. Add an additional Linker Command file to your project. From E:\C281x\Labs\Lab5A add: Lab5A.cmd Open and inspect this file. You will see that we add just one entry for the physical memory location (ROM) in data page 1 and that we connect the memory area IQmathTables to address ROM. The attribute NOLOAD assures that the debugger will not try to download this area into the DSP when we load the program because it is already there, it is ROM read only memory. 21. Modify T1_Compare_isr( ) This interrupt service routine is a good point to modify the pulse width of the PWM signal. Recall, we do have now a global array sine_table[512] that holds all the sine values we need for our calculation. Now we have to do a little bit of maths. What is the relationship between this sine value and the value of T1CMPR? Answer: (1) We know that the difference between T1PR and T1CMPR defines the pulse width of the current PWM period. So the goal is to calculate a new value for T1CMPR. (2) Next, we have to take into account that the sine table delivers signed values between +1 and 1. Therefore we have to add an offset of +1.0 to this value. (3) This shifted sine value has to be multiplied with T1PR/2. Summary:

T 1PR T 1CMPR = T 1PR (sin e _ table[index ] + 1.0 ) * 2

To code this into the IQ-Math form we use: T1CMPR = T1PR - _IQ30mpy(sine_table[index] + _IQ30(0.9999),T1PR/2) _IQ30mpy(a,b) is an intrinsic function call to do a multiplication in IQ30-Format. The value from sine_table is already in IQ30-format, whereas the constant 1.0 has to be translated into it by function call _IQ30(0.9999).

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Lab 5A: Generate a PWM sine wave

To avoid fixed-point overflows we can embed the calculation into a saturation function _IQsat(x,max,min) to limit the result between T1PR and 0. This leads to our final instruction: EvaRegs.T1CMPR = EvaRegs.T1PR _IQsat( _IQmpy( sine_table[index] + _IQ30(0.9999), EvaRegs.T1PR/2), EvaRegs.T1PR,0) ; Add this line just after the EDIS instruction that follows the service of the Watchdog timer. 22. Setup the sine wave frequency. Recall that the Boot ROM sine table consists of 512 entries for a unit circle. The frequency of the sine wave is given by:

f SIN =

f PWM Number of PWM - periods per 360

For example, if we use all 512 entries of the Boot ROM table we get:

f SIN =

50 KHz = 97,6 Hz 512

If we use only one lookup table entry out of 4, we end up with:

f SIN =

50 KHz = 390,6 Hz 128

Lets use this last set up. It means we have to increment the index by 4 to make the next access to the lookup table. Add the next line after the update line for T1CMPR: index += 4; Do not forget to: (1) Reset variable index to 0 if it is increased above 511. (2) Declare the integer variable index to be static.

Build and Load

23. Click the Rebuild All button or perform: Project Build

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Optional Exercise

and watch the tools run in the build window. If you get syntax errors or warnings debug as necessary. 24. Load and test the final version of the output file as youve done before. With the help of the oscilloscope we should see now a change of the pulse width of the PWM signal on the fly. 25. Optional: Low pass filter: The low pass filter capacity of the tiny loudspeaker is not strong enough to integrate the pulse sequence to a sine wave shaped signal. We can improve this by adding a simple low-pass filter between the two connectors of jumper JP7-2 (DSP-T1PWM) and JP7-1 (Loudspeaker). Build a passive low pass filter of first order with a frequency of 25 KHz:

f Filter =

1 = 25 KHz 2 R C

Optional Exercise
How about other frequencies?
In the previous exercise we generated a modulated sine wave of 390 Hz. We used the 512-point look-up table and stepped through it using an increment of 4. How do we generate other frequencies? Answer: when we change the step size for variable index we can generate more (or less PWM-periods per 360. More means we slow down the sine frequency, less means we increase the sine wave frequency. The following table shows the different sine wave frequencies for a PWM carrier frequency of 50 KHz and a lookup table of 512 points per 360:

f SIN =

f PWM Number of PWM - periods per 360

Number of PWM periods per 360 512 256 171 128 102 51 34 26 10 Sine wave frequency In Hz 97.6 195.3 293 390 488 976 1,460 1,950 4,880

Incremental step of index 1 2 3 4 5 10 15 20 50

We cant increase the step size much above 50 because this gives us only 10 points per 360 to synthesize the sine wave.

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Optional Exercise

What about frequencies that we do not match with any of these incremental steps? Recall our Lab Exercise 5 with the range of 8 notes; it started with a note of 264Hz. How do we generate a sine wave of 264 Hz? The answer is: We have to modify the PWM frequency itself. So far we did all experiments with a fixed PWM signal of 50 KHz. Lets fix now the number of points taken out of the look up table to 128 (that is an index increment by 4). To get a sine wave of 264Hz we calculate:

f SIN =

f PWM = 264 Hz 128

f PWM = 264 Hz *128 = 33,792 KHz

To setup a PWM signal of 33,792 KHz we have to re-calculate T1PR:

f PWM =

f CPU T 1PR TPST 1 HISCP

T 1PR =

150 MHz = 2,219.46 33.792 KHz 1 2

T1PR has to be loaded with an integer value, so we have to round the result to 2219. Test:

f PWM =

f CPU 150 MHz = = 33.799 KHz T 1PR TPST 1 HISCP 2219 *1* 2
f PWM 33.799 KHz = = 264.05 Hz 128 128

f SIN =

Thats a reasonable result; the intended frequency of 264Hz is missed by an error of 0.02%.

26. Try to setup your code to generate a sine wave of 264Hz! 27. If you have additional time in your laboratory try to improve Lab5 to generate all 8 notes with sine wave modulated PWMs!

End of Lab 5A

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Optional Exercise

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