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VLSI - P Well Process

CMOS fabrication uses both N-type and P-type devices on the same chip. There are two main CMOS technologies: P-well and N-well. In P-well technology, the substrate is N-type and the P-channel device is built directly on the substrate while the N-channel device is built into a P-type well. In N-well technology, the substrate is P-type and the N-channel device is built directly on the substrate while the P-channel device is built into an N-type well. Advanced technologies include twin tub, which uses both N-wells and P-wells on a lightly doped N-type substrate, and silicon-on-ins

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5K views15 pages

VLSI - P Well Process

CMOS fabrication uses both N-type and P-type devices on the same chip. There are two main CMOS technologies: P-well and N-well. In P-well technology, the substrate is N-type and the P-channel device is built directly on the substrate while the N-channel device is built into a P-type well. In N-well technology, the substrate is P-type and the N-channel device is built directly on the substrate while the P-channel device is built into an N-type well. Advanced technologies include twin tub, which uses both N-wells and P-wells on a lightly doped N-type substrate, and silicon-on-ins

Uploaded by

K.R.Raguram
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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CMOS FABRICATION

CMOS: CMOS Technology depends on using both N-Type and P-Type devices on the same chip. The two main technologies: P-Well: The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate. N-Well: The substrate is P-Type. The N-channel device is built directly on the substrate, while the P-channel device is built into a N-type well within the parent P-Type substrate.

ADVANCED TECHNOLOGIES:
Twin Tub

Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate.

Silicon-on-Insulator (SOI) CMOS Process

SOI allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.

P WELL PROCESS
STEP 1:

A moderately doped n-type substrate ic taken.

N-SUBSTRATE

STEP 2: P-well is formed by ion Implantation and diffusion. The depth of the p-well depends on the level of diffusion. Normally shallow well is preferred. Other areas are masked with Field Oxide(FOX).

SiO2 P-Well N-SUBSTRATE

STEP 3: Active masks are placed over the substrate, it defines the places for gate, source, drain implantation

SiO2
P-Well N-SUBSTRATE

STEP4: The oxide layer is protected by the protection ring consisting of SiN.

P-Well
N-SUBSTRATE

STEP5: Photo resist mask is used to mask the p-well from P+ implantation.

Photo Resistive Mask

P-Well
N-SUBSTRATE

STEP 6:

P+ Implantation

P+

n+

P-Well N-SUBSTRATE

STEP 7: Polysilicon coating in done, gate and source points are marked and other areas are itched out.

Polysilico n
Oxide Layer

P-Well
N-SUBSTRATE

STEP 8: Next is occurrence of p+ regions.

p+

p+

P-Well

N-SUBSTRATE

STEP 9:

Now n+ diffusion is done by masking the required area.

p+

p+

P-Well N-SUBSTRATE

p+

p+

n+ P-Well

n+

N-SUBSTRATE

STEP 10:

METALIZATION

METAL n+ P-Well n+

p+

p+

N-SUBSTRATE

THANK YOU!

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