ModelSim Tutorial Brief
ModelSim Tutorial Brief
if you select Create File choose VERILOG Type of file in the dropbox menu, bcoz all file shoud have .v extension
4. Write code into your files. Left window shows your project and right window shows your code.
6. Errors in compilation are written in lower window. Double clicking on error will give you detailed list of errors.
7. Once you have compiled your code, we simulate it to check functionality (testing). Switch to library tab in left window. Your compiled modules are in your library work (added to work when project was created).
8. Load your testbench for simulation. Remember only testbench can run not all modules that you write.
To run, select Simulate->Run->Run All You will see the output in lower window.
10.Another way to simulate is through waveform. Load your testbench or module. Add your signals to wave.
Select all the signals (input and output signals). Right click and select Add to Wave > Selected Signals. This will add all the signals to wave. 11. Assign value to signals by clicking create/Modify waveform.
Wave output
Note: to see the output waveform click Create/Modify waveform window->select constant pattern->click next without changing the value click finish. 12.Happy Coding , removing compilation error and most importantly debugging !!!!!!!!