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CMOS Fabrication 1

The document describes the process for fabricating a CMOS device using N-well technology on a P-type silicon substrate. The key steps include: 1) Depositing silicon nitride and using a photolithography process with an N-well mask to implant N-type dopants and create N-well regions. 2) Using an active area mask and channel stopper mask in conjunction to implant P-type dopants and create channel stopper regions between N-wells. 3) Growing gate oxides, depositing polysilicon for gates, and using masks to pattern the gates and implant N-type and P-type dopants to create sources and drains. 4) Depositing

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53 views47 pages

CMOS Fabrication 1

The document describes the process for fabricating a CMOS device using N-well technology on a P-type silicon substrate. The key steps include: 1) Depositing silicon nitride and using a photolithography process with an N-well mask to implant N-type dopants and create N-well regions. 2) Using an active area mask and channel stopper mask in conjunction to implant P-type dopants and create channel stopper regions between N-wells. 3) Growing gate oxides, depositing polysilicon for gates, and using masks to pattern the gates and implant N-type and P-type dopants to create sources and drains. 4) Depositing

Uploaded by

ssmande
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CMOS Fabrication

Sudhakar Mande

N well Technology We start with lightly doped P type substrate

Top View

Cross section

Silicon nitride is deposited

Top View

Cross section

N- well Mask mask #1

Top View

Cross section

Photolithography 1.Apply photo resist 2. Place N-well Mask 3. Ultra-violet exposure 4. Develop of photo resist

N-Well Mask Photo resist Si3N4

Silicon substrat

After exposure

N-Well Mask Photo resist Si3N4

substrate

Photo resist Development

Photo resist Si3N4

substrate

Silicon Nitride Etching

Photo resist Si3N4

substrate

N- Well Implant

Photo resist Si3N4

substrate

Photo resist is stripped Si3N4 is etched

Si3N4 is Deposited

Mask #2 Active Area Mask

Si3N4 is Deposited

After ultra violet exposure

Photo resist development

Photo resist development

Channel Stopper Mask (Complement of N well Mask)

Top View

Cross Section

Mask # 3 Channel Stopper Mask Lithography

Photo resist Development

P+ channel stopper implant

SiO2 is grown using wet oxidation

Photo-resist and Si3N4 is removed

Thin Gate Oxide is grown using Dry oxidation

Polysilicon is deposited

Mask # 4 Poly Silicon Gate Mask

Top View

Cross Section

Polysilicon is deposited

After ultra-violet exposure

Photo resist Development

Etch Polysilicon

Photolithography for N+ Mask

Mask 5 N + Mask

After Ultraviolet Radiation

Photo resist Development

Photo resist Development

N+ Implant

P+ Implant

P+ Implant

Photo resist removed

Deposit Oxide

Mask #6 Contact Mask

After ultra violet exposure

Photo resist Development and Etching

Metal is Deposited

Mask #7 After Photolithography

Mask #6 Metallization Mask Input

GND

Output

VDD

Surface is covered with passivation layer

Last Mask: Bonding Mask

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