CHAPTER 12

Exercises
E12.1 (a) vGS = 1 V and vDS = 5 V: Because we have vGS < Vto, the FET is in cutoff. (b) vGS = 3 V and vDS = 0.5 V: Because vGS > Vto and vGD = vGS vDS = 2.5 > Vto, the FET is in the triode region. (c) vGS = 3 V and vDS = 6 V: Because vGS > Vto and vGD = vGS vDS = 3 V < Vto, the FET is in the saturation region. (d) vGS = 5 V and vDS = 6 V: Because vGS > Vto and vGD = vGS vDS = 1 V which is less than Vto, the FET is in the saturation region. E12.2 First we notice that for v GS = 0 or 1 V, the transistor is in cutoff, and the drain current is zero. Next we compute the drain current in the saturation region for each value of vGS: 1 1 K = 2 KP (W / L) = 2 (50 10 6 )(80 / 2) = 1 mA/V 2

iD = K (v GS Vto ) 2

The boundary between the triode and saturation regions occurs at v DS = v GS Vto

v GS (V)
2 3 4

iD (mA)
1 4 9

v DS at boundary
1 2 3

In saturation, iD is constant, and in the triode region the characteristics are parabolas passing through the origin. The apex of the parabolas are on the boundary between the triode and saturation regions. The plots are shown in Figure 12.7 in the book.
E12.3

First we notice that for v GS = 0 or 1 V, the transistor is in cutoff, and the drain current is zero. Next we compute the drain current in the saturation region for each value of vGS:

1 1 K = 2 KP (W / L) = 2 (25 10 6 )(200 / 2) = 1.25 mA/V 2 iD = K (v GS Vto ) 2

The boundary between the triode and saturation regions occurs at v DS = v GS Vto .

v GS (V)
2 3 4

iD (mA)
1.25 5 11.25

v DS at boundary
1 2 3

In saturation, iD is constant, and in the triode region the characteristics are parabolas passing through the origin. The apex of the parabolas are on the boundary between the triode and saturation regions. The plots are shown in Figure 12.9 in the book.
E12.4

We have

v GS (t ) = v in (t ) +VGG = sin(2000t ) + 3
Thus we have VGS max = 4 V, VGSQ = 3 V, and VGS min = 2 V. The characteristics and the load line are:

For vin = +1 we have vGS = 4 and the instantaneous operating point is A. Similarly for vin = 1 we have vGS = 2 V and the instantaneous operating point is at B. We find VDSQ 11 V, VDS min 6 V, VDS max 14 V.
E12.5

First, we compute

R1 + R2 1 1 and K = 2 KP ( / L) = 2 (50 10 6 )(200 / 10) = 0.5 mA/V 2 W

As in Example 12.2, we need to solve: VG 1 2 V V V 2 VGSQ + R K 2 to GSQ + ( to ) R K = 0 S S Substituting values, we have
2 VGSQ VGSQ 6 = 0

VG = VDD

R2

= 7V

The roots are VGSQ = 2 V and 3 V. The correct root is VGSQ = 3 V which yields IDQ = K(VGSQ Vto)2 = 2 mA. Finally, we have VDSQ = VDD RSIDQ = 16 V.
E12.6

First, we replace the gate bias circuit with its equivalent circuit:

Then we can write the following equations:

1 1 K = 2 KP (W / L) = 2 (25 10 6 )(400 / 10) = 0.5 mA/V 2

VGG = 11.5 =VGSQ Rs I DQ + 20

(1) 3

I DQ = K ( GSQ Vto ) 2 V

(2)

Using Equation (2) to substitute into Equation (1), substituting values, and 2 rearranging, we have VGSQ 16 = 0 . The roots of this equation are

VGSQ = 4 V. However VGSQ = 4 V is the correct root for a PMOS

transistor. Thus we have I DQ = 4.5 mA and

VDSQ = Rs I DQ + RD I DQ 20 = 11 V.

E12.7

From Figure 12.21 at an operating point defined by VGSQ = 2.5 V and VDSQ = 6 V, we estimate

gm =

iD (4.4 1.1) mA = 3.3 mS = v GS 1V

1 rd =

Taking the reciprocal, we find rd = 20 k.

iD (2.9 2.3) mA = 0.05 10 3 (14 - 2) V v GS

E12.8

gm =

iD v GS

=
Q po int

v GS

K (v GS Vto )2
Q po int

= 2K V GSQ Vto

E12.9

RL =

1 rd + 1 RD + 1 RL

= RD = 4.7 k

Avoc = gm RL = (1.77 mS) (4.7 k ) = 8.32

E12.10

For simplicity we treat rd as an open circuit and let RL = RD RL.

v in = v gs + Rs gmv gs v o = RL gmv gs Av =
E12.11

RL gm vo = v in 1 + RL gm

RL = RD RL = 3.197 k

Av =
E12.12

RL gm vo (3.197 k )(1.77 mS) = = = 0.979 1 + (2.7 k )(1.77 mS) v in 1 + RL gm

The equivalent circuit is shown in Figure 12.28 in the book from which we can write

v in = 0

v gs = v x
Ro =

ix =

vx vx v v + gmv gs = x + x + gmv x RS rd RS rd

Solving, we have

vx 1 = 1 1 ix gm + + RS rd

E12.13

Refer to the small-signal equivalent circuit shown in Figure 12.30 in the book. Let RL = RD RL . v in = v gs

v o = RL gmv gs Av = v o v in = RL gm iin = v in Rs gmv gs = v in Rs + gmv in Rin = v in 1 = iin gm + 1 Rs

If we set v (t) = 0, then we have vgs = 0. Removing the load and looking back into the amplifier, we see the resistance RD. Thus we have Ro = RD .
E12.14 E12.15

See Figure 12.34 in the book. See Figure 12.35 in the book.

Answers for Selected Problems

P12.3*

(a) Saturation iD = 2.25 mA (b) Triode iD = 2 mA (c) Cutoff iD = 0

P12.4*

iD

vGS = 4 V

3V

2V

vDS
P12.11* Vto = 1.5 V K = 0.8 mA/V2 P12.15* v GS = 2.5 V P12.17*

The load line rotates around the point (VDD, 0) as the resistance changes.
P12.19* The gain is zero. P12.21* RDmax = 3.778 k

P12.27* IDQ = 3.432 mA VDSQ = 16.27 V P12.28* RS = 3 k

R2 = 2 M
P12.29* Rs = 400

R1 = 2.583M.

P12.34* VDSQ = VGSQ = 5.325 V IDQ = 4.675 mA P12.40* gm = 2KVDSQ P12.41* rd = P12.50* (a)

2K ( GSQ V

1 Vto VDSQ )

VGSQ = 3 V I DQ = 10 mA gm = 0.01 S Av = 5 Rin = 255 k Ro = 1 k

1 = 253 1 RD + gm

(b)

P12.53* Ro =

P12.56* RS = 3.382 k

Av = 0.6922

Rin = 666.7k
Ro = 386.9

Practice Test
T12.1

Drain characteristics are plots of iD versus vDS for various values of vGS. First, we notice that for v GS = 0.5 V, the transistor is in cutoff, and the

drain current is zero, because vGS is less than the threshold voltage Vto. Thus, the drain characteristic for v GS = 0.5 V lies on the horizontal axis.

Next, we compute the drain current in the saturation region for v GS = 4 V.

1 1 K = 2 KP (W / L) = 2 (80 10 6 )(100 / 4) = 1 mA/V 2

iD = K (v GS Vto ) 2 = K (4 1) 2 = 9 mA for v DS > v GS Vto = 3 V

Thus, the characteristic is constant at 9 mA in the saturation region. The transistor is in the triode region for v DS < v GS Vto = 3 V, and the drain current (in mA) is given by iD = K[2(vGS Vto)vDS vDS2] = 6vDS vDS2 with vDS in volts. This plots as a parabola that passes through the origin and reaches its apex at iD = 9 mA and v DS = 3 V. The drain characteristic for vGS = 4 V is identical to that of Figure 12.11 in the book.
T12.2

We have v GS (t ) = v in (t ) +VGG = sin(2000t ) + 3 V. Thus, we have VGS max = 4 V, VGSQ = 3 V, and VGS min = 2 V. Writing KVL around the drain circuit, we have

VDD = RD iD + v DS

With voltages in volts, currents in mA, and resistances in k, this becomes 10 = 2iD + v DS which is the equation for the load line. The characteristics and the load line are:

The results of the load-line analysis are VDSmin 1.0 V, VDSQ 2.05 V, and VDSmax 8.2 V.
T12.3

Because the gate current is zero, we can apply the voltage division principle to determine the voltage at the gate with respect to ground. 10 k 12 = 3 V VG = (10 + 30) k For the transistor, we have 1 1 K = 2 KP (W / L) = 2 (80 10 6 )(100 / 4) = 1 mA/V 2 Because the drain voltage is 12 V, which is higher than the gate voltage, we conclude that the transistor is operating in the saturation region. Thus, we have I DQ = K ( GSQ Vto ) 2 V

I DQ = ( GSQ 1) 2 = 0.5 mA V
Solving, we have VGSQ = 1.707 V or VGSQ = 0.293 V. However, VGSQ must be larger than Vto for current to flow, so the second root is extraneous. Then, the voltage across Rs is VS = VG VGSQ = 1.293 V. The current through RS is IDQ. Thus, the required value is RS = 1.293 / 0.5 = 2.586 k.

10

T12.4

This transistor is operating with constant vDS. Thus, we can determine gm by dividing the peak ac drain current by the peak ac gate-to-source voltage. iD 0.05 mA = = 2.5 mS gm = v GS v =V 0.02 V
DS DSQ

The Q-point is VDSQ = 5 V, VGSQ = 2 V, and I DQ = 0.5 mA.

T12.5

(a) A dc voltage source is replaced with a short circuit in the small-signal equivalent. (b) A coupling capacitor becomes a short circuit. (c) A dc current source is replaced with an open circuit, because even if an ac voltage appears across it, the current through it is constant (i.e., zero ac current flows through a dc current source). See Figure 12.31(b) and (c) in the text.

T12.6

11