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Verilog

The document describes different types of adders and subtractors using Verilog code. It defines a full adder module that takes two input bits (a and b) and a carry bit (c) as input and produces a sum and carry output. It also defines half adder, half subtractor, and full subtractor modules for performing basic binary arithmetic operations.

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36 views2 pages

Verilog

The document describes different types of adders and subtractors using Verilog code. It defines a full adder module that takes two input bits (a and b) and a carry bit (c) as input and produces a sum and carry output. It also defines half adder, half subtractor, and full subtractor modules for performing basic binary arithmetic operations.

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roopam_wonder
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Full adder

module full_add(a, b, c, sum, carry); input a; input b; input c; output sum; output carry; wire an,bn,z0,z1,z2; not(a,an); not(b,bn); xor(sum,a,b,c); and(z0,a,b); and(z1,an,b,c); and(z2,a,bn,c); or(carry,z0,z1,z2); endmodule

half adder:
module half_add(a, b, sum, carry); input a; input b; output sum; output carry; xor(sum,a,b); and(carry,a,b); endmodule

half subtracter:
module half_sub(a, b, diff, borrow); input a; input b; output diff;

output borrow; wire an; not(an,a); xor(diff,x,y); and(borrow,an,b); endmodule

Full substractor:
module full_sub(x, y, z, b, d); input x; input y; input z; output b; output d; wire xn,yn,z0,z1,z2,y0,y1,y2; not(xn,x); not(yn,y); and(z0,xn,yn,z); and(z1,xn,y,z); and(z2,x,yn,zn); and(z3,x,y,z); or(d,z0,z1,z2,z3); and(y0,xn,y); and(y1,xn,z); and(y2,y,z); or(b,y0,y1,y2); endmodule

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