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Experiment No. 1: A) The AND Operation

The document describes an experiment to implement VHDL code for 2, 3, and 4 input AND, OR, XOR, and XNOR gates. The VHDL code is written and tested in a Mentor Graphics FPGA Advantage tool with ModelSim. Truth tables are provided for each gate and input combination. VHDL code is provided for each gate and input scenario. The output is a result window showing the simulation of each gate.

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Rohit Panwar
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110 views

Experiment No. 1: A) The AND Operation

The document describes an experiment to implement VHDL code for 2, 3, and 4 input AND, OR, XOR, and XNOR gates. The VHDL code is written and tested in a Mentor Graphics FPGA Advantage tool with ModelSim. Truth tables are provided for each gate and input combination. VHDL code is provided for each gate and input scenario. The output is a result window showing the simulation of each gate.

Uploaded by

Rohit Panwar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT No.

1
Aim:
To implement VHDL code for 2,3,4,inputs AND, OR, XOR and XNOR Gates and testing their simulation with signals.

Apparatus Required:
a) Mentor Graphics FPGA Advantage with PS 8.1, ModelSim SE 6.3a

Theory:
A) The AND Operation The AND Operation is defined as: The output of an AND gate is 1 if and only of all the inputs are 1. Mathematically, it is written as: Y= A AND B AND C.AND N = A.B.C..N Where A,B,C..N are input variables and Y is the output variable. Symbol:

Truth Table: 1) 2- Input AND Gate A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1

2) 3- Input AND Gate

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 0 0 0 0 0 0 1

B) The OR Operation The OR Operation is defined as: The output of an OR gate is 1 if and only if one or more input are 1. Mathematically, it is written as: Q= A OR B OR C.OR N = A+B+C+..+N Where A,B,C..N are input variables and Y is the output variable. Symbol:

Truth Table: 1) 2- Input OR Gate A 0 0 1 1 B 0 1 0 1 Q 0 1 1 1

2) 3- Input OR Gate

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Q 0 1 1 1 1 1 1 1

C) The XOR Operation The XOR Operation is widely used in digital circuits. It is not a basic operation and can be performed using the basic gates- AND, OR and NOT or universal gates NAND and NOR. Mathematically, it is written as: Y= A XOR B XOR C..XOR N Symbol:

Truth Table: 1) 2- Input XOR Gate A 0 0 1 1 B 0 1 0 1 Q 0 1 1 0

2) 3- Input XOR Gate

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Q 0 1 1 0 1 0 0 1

D) The XNOR Operation The XNOR Operation is widely used in digital circuits. It is not a basic operation and can be performed using the basic gates- AND, OR and NOT or universal gates NAND and NOR. Mathematically, it is written as: Y= A XNOR B XNOR C..XNOR N Symbol:

Truth Table: 1) 2- Input XNOR Gate A 0 0 1 1 B 0 1 0 1 Y 1 0 0 1

2) 3- Input XNOR Gate A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 1 0 0 1 0 1 1 0

1) 2- Input AND Gate

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY And_2 IS port(A,B: IN std_logic;Y: OUT std_logic); END ENTITY And_2; -ARCHITECTURE And_2_A OF And_2 IS BEGIN Y<=A AND B; END ARCHITECTURE And_2_A; Output:

Result window of 2 Input AND gate

2) 3- Input AND Gate

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY And_3 IS port(A,B,C: IN std_logic; Y: OUT std_logic); END ENTITY And_3; -ARCHITECTURE And_3_A OF And_3 IS BEGIN Y<= A AND B AND C; END ARCHITECTURE And_3_A; Output:

Result Window of 3 Input AND gate

3) 4- Input AND Gate

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY And_4 IS port(A,B,C,D: IN std_logic; Y: OUT std_logic); END ENTITY And_4; -ARCHITECTURE And_4_A OF And_4 IS BEGIN Y<= A AND B AND C AND D; END ARCHITECTURE And_4_A; Output:

Result Window of 4 input AND Gate

4) 2- Input OR Gate

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Or_2 IS port(A,B: IN std_logic; Y: OUT std_logic); END ENTITY Or_2; -ARCHITECTURE Or_2_A OF Or_2 IS BEGIN Y<= A OR B; END ARCHITECTURE Or_2_A; Output:

Result Window of 2 input OR Gate

5) 3- Input OR Gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Or_3 IS port(A,B,C: IN std_logic;Y: OUT std_logic); END ENTITY Or_3; -ARCHITECTURE Or_3_A OF Or_3 IS BEGIN Y<= A OR B OR C END ARCHITECTURE Or_3_A; Output:

Result Window of 3 input OR Gate

6) 4- Input OR Gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Or_4 IS port(A,B,C,D: IN std_logic; Y: OUT std_logic); END ENTITY Or_4; -ARCHITECTURE Or_4_A OF Or_4 IS BEGIN Y<=A OR B OR C OR D; END ARCHITECTURE Or_4_A; Output:

Result Window of 4 Input OR Gate

7) 2- Input XOR Gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Xor_2 IS port(A,B: IN std_logic; Y: OUT std_logic); END ENTITY Xor_2; -ARCHITECTURE Xor_2_A OF Xor_2 IS BEGIN Y<= A XOR B; END ARCHITECTURE Xor_2_A; Output:

Result Window of 2 input XOR Gate

8) 3- Input XOR Gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Xor_3 IS port(A,B,C: IN std_logic; Y: OUT std_logic); END ENTITY Xor_3; -ARCHITECTURE Xor_3_A OF Xor_3 IS BEGIN Y<= A XOR B XOR C; END ARCHITECTURE Xor_3_A; Output:

Result Window of 3 input XOR Gate

9) 4- Input XOR Gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Xor_4 IS port(A,B,C,D:IN std_logic; y: OUT std_logic); END ENTITY Xor_4; -ARCHITECTURE Xor_4_A OF Xor_4 IS BEGIN Y<= A XOR B XOR C XOR D; END ARCHITECTURE Xor_4_A;

Output:

Result Window of 4 input XOR Gate

10) 2- Input XNOR Gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Xnor_2 IS port(A,B: IN std_logic; Y: OUT std_logic); END ENTITY Xnor_2; -ARCHITECTURE Xnor_2_A OF Xnor_2 IS BEGIN Y<= A XNOR B; END ARCHITECTURE Xnor_2_A; Output:

Result Window of 2 input XNOR Gate

11) 3- Input XNOR Gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY three_input_xnor IS port (A, B, C: IN std_logic ; Y: OUT std_logic); END ENTITY three_input_xnor; -ARCHITECTURE three_input_xnor_data OF three_input_xnor IS BEGIN Y<= NOT(A XOR B XOR C); END ARCHITECTURE three_input_xnor_data; Output:

Result Window of 3 Input XNOR Gate

12) 4- Input XNOR Gate LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY four_input_xnor IS port (A, B, C, D: IN std_logic ; Y: OUT std_logic); END ENTITY four_input_xnor; -ARCHITECTURE four_input_xnor_data OF four_input_xnor BEGIN Y<= NOT(A XOR B XOR C XOR D); END ARCHITECTURE four_input_xnor_data; Output:

Result Window of 4 Input XNOR Gate

Result:
VHDL code for 2, 3, 4 input AND, OR, XOR and XNOR gates were implemented and their simulation were tested.

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