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Decade Counter

The document describes implementing a VHDL code for a decade counter. It includes the aim, theory on counters and decade counters, a truth table and timing diagram. It also provides the VHDL code for a down counter with an entity, architecture, process, and outputs. The result is that the VHDL code for a decade counter was implemented and simulated successfully.

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Rohit Panwar
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313 views4 pages

Decade Counter

The document describes implementing a VHDL code for a decade counter. It includes the aim, theory on counters and decade counters, a truth table and timing diagram. It also provides the VHDL code for a down counter with an entity, architecture, process, and outputs. The result is that the VHDL code for a decade counter was implemented and simulated successfully.

Uploaded by

Rohit Panwar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT NO.

12
Aim
To implement VHDL code for Decade Counter

Tool required
Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a

Theory

Counter
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal.

Decade Counter
A decade counter is one that counts in decimal digits, rather than binary. A decade counter may have each digit binary encoded (that is, it may count in binary-coded decimal, as the7490 integrated circuit did) or other binary encodings (such as the bi-quinary encoding of the7490 integrated circuit).

Fig (12.1)

Truth Table
TABLE (12.1)

CLOCK 0 1 2 3 4 5 6 7 8 9 10

E 0 0 0 0 0 0 1 1 1 1 0

D 0 0 0 1 1 1 0 0 1 1 0

C 0 0 1 0 0 1 0 0 0 1 0

B 0 1 1 1 1 1 1 1 0 1 0

A 0 1 1 0 1 0 0 1 0 1 0

Timing Diagram

VHDL code for down counter


LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; ENTITY decade IS port(cr,pr,clk:in std_logic; q:inout std_logic_vector(0 to 4)); END ENTITY decade; ARCHITECTURE decade_beh OF decade IS signal temp:std_logic_vector(0 to 4); BEGIN process(cr,pr,clk) begin if(cr='0')then temp<="00000"; elsif(pr='0')then temp<="11111"; elsif(clk='1' and clk 'event)then if(temp="00000")then temp<="00011"; elsif(temp="00011")then temp<="00111"; elsif (temp="00111")then temp<="01010"; elsif(temp="01010")then temp<="01011"; elsif(temp="01011")then temp<="01110"; elsif(temp="01110")then

temp<="10010"; elsif(temp="10010")then temp<="10011"; elsif(temp="10011")then temp<="11000"; elsif(temp="11000")then temp<="11111"; end if; end if; end process; END ARCHITECTURE decade_beh;

Output

Result window of decade counter

Result - The VHDL code for Decade counter were implemented and simulated successfully.

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