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The document describes three Verilog code modules: 1) A 1-bit full adder module that takes two 1-bit inputs (a and b) and a carry-in (cin) and produces a sum (s) and carry-out (cout). 2) A 4-bit full adder module that uses four instances of the 1-bit full adder module to add four 1-bit inputs (a and b) and a carry-in and produces a 4-bit sum and carry-out. 3) A 2-to-4 decoder module that takes a 2-bit input (a) and uses NOT gates and AND gates to decode it into a 4-bit output (

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Bilal Ahmad
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52 views5 pages

Lab 02 Submitted To

The document describes three Verilog code modules: 1) A 1-bit full adder module that takes two 1-bit inputs (a and b) and a carry-in (cin) and produces a sum (s) and carry-out (cout). 2) A 4-bit full adder module that uses four instances of the 1-bit full adder module to add four 1-bit inputs (a and b) and a carry-in and produces a 4-bit sum and carry-out. 3) A 2-to-4 decoder module that takes a 2-bit input (a) and uses NOT gates and AND gates to decode it into a 4-bit output (

Uploaded by

Bilal Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Name: Reg no.

Section

Bilal Ahmad EE 307-165r A

Lab Submitted To :

02
SIR FAHAD ISLAM CHEEMA

DDl

Lab

1 bit full adder :


module onebitfulladder(s,cout,a,b,cin); input a,b,cin; output s,cout; assign {cout,sim}=a+b+cin; endmodule

Data Flow Modeling

4 bit full adder : Data Flow Modeling


Code: module fourbitfulladder(s,cout,a,b,cin); input[3:0] a,b; input cin; output[3:0]s; output cout; wire[2:0] c; onebitfulladder fa1(s[0],c[0],a[0],b[0],cin); onebitfulladder fa2(s[1],c[1],a[1],b[1],c[0]); onebitfulladder fa3(s[2],c[2],a[2],b[2],c[1]); onebitfulladder fa4(s[3],cout,a[3],b[3],cout); endmodule

2 into 4 bit decoder using an array: Data flow


Modeling
Code: module TwointoFourbitdecoderusinganarray(o,a); input[1:0]a; output[3:0]o; wire [1:0]w; not n1(w[0],a[0]); not n2(w[1],a[1]); and a1(o[0],a[0],a[1]); and a2(o[1],a[1],w[0]); and a3(o[2],w[1],a[0]); and a4(o[3],w[1],w[0]); endmodule

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