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Lab 01 Submitted To

This document contains Verilog code for implementing half adders, full adders using half adders, and a four bit full adder using four full adders. It defines modules for a half adder with inputs a and b and outputs s (sum) and c (carry), a full adder using two half adders with inputs a, b, cin and outputs s and cout, and a four bit full adder using four full adders with inputs for four bits each of a and b and an input cin and outputs for the sum of each bit s1-s4 and the final carry out cout.

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Bilal Ahmad
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56 views4 pages

Lab 01 Submitted To

This document contains Verilog code for implementing half adders, full adders using half adders, and a four bit full adder using four full adders. It defines modules for a half adder with inputs a and b and outputs s (sum) and c (carry), a full adder using two half adders with inputs a, b, cin and outputs s and cout, and a four bit full adder using four full adders with inputs for four bits each of a and b and an input cin and outputs for the sum of each bit s1-s4 and the final carry out cout.

Uploaded by

Bilal Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Name: Reg no.

Section

Bilal Ahmad EE 307-165r A

Lab Submitted To :

01
SIR FAHAD ISLAM CHEEMA

DDl

Lab

Half Adder:
Code: module Halfadder(s,c,a,b); input a,b; output s,c; and a1(c,a,b); xor x1(s,a,b); endmodule

Gate Level Modeling

Full adder using two half adders (one bit full adder) :
Code: module Fulladderusingtwohalfadders(s,cout,a,b,cin); input a,b,cin; output s,cout; wire s1,c1,c2; Halfadder ha1(s1,c1,a,b); Halfadder ha2(s,c2,s1,cin); or (cout,c1,c2); endmodule

Four bit full adder using four full adders:


Code: module Fourbitffulladderusingfourfulladders(s1,s2,s3,s4,cout,cin,a1,b1,a2,b2,a3,b3,a4,b4); input cin,a1,b1,a2,b2,a3,b3,a4,b4; output s1,s2,s3,s4,cout; wire c1,c2,c3; Fulladderusingtwohalfadders fa1(c1,s1,cin,a1,b1); Fulladderusingtwohalfadders fa2(c2,s2,c1,a2,b2); Fulladderusingtwohalfadders fa3(c3,s3,c2,a3,b3); Fulladderusingtwohalfadders fa4(cout,s4,c3,a4,b4); endmodule

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