ECEN4618: Experiment #1 Timing circuits with the 555 timer

c 1998 Dragan Maksimovi c Department of Electrical and Computer Engineering University of Colorado, Boulder

The purpose of this lab assignment is to examine operating principles and several practical applications of the 555 integrated-circuit timer. The 555 is capable of producing accurate time delays or oscillations. These functions are needed in many analog, digital or mixed-signal applications. The circuits you design and test in this lab assignment will be applied as building blocks in the lab assignments that follow.

1 The 555 Timer

A functional block diagram of the 555 timer is shown in Fig. 1. Various timing functions can be obtained by connecting resistors and capacitors around the 555. The 555 consists of two voltage comparators (C 1 and C 2), an R-S ip-op FF, a discharge transistor Q14 , a resistive voltage divider (R3 , R4 , R5 ), and an output buffer. The (,) input of the voltage comparator C 1 is internally connected to the resistive voltage divider. The voltage at the (,) input is equal to VH = 2VCC =3, which is called the threshold level. The (+) input of the comparator C 1 is connected to the external THRESHOLD pin (pin 6). The (+) input of the voltage comparator C 2 is connected to VL = VCC =3, which is called the trigger level, while the (,) input is the external TRIGGER pin (pin 2). The (,) input of the voltage comparator C 1 is also available as the CONTROL pin (pin 5), which can be used for external adjustment of the threshold and trigger levels. The comparator C 1 and C 2 outputs are the reset R and the set S inputs, respectively, for the ip-op. When the TRIGGER input falls bellow the trigger level VL , the output of the voltage comparator C 2 goes high and sets the ip-op. If the TRIGGER input is above the trigger level, and the THRESHOLD input is above the threshold level, the output of the voltage comparator C 1 is high and the ip-op is reset. The ip-op output Q drives the discharge transistor Q14 , and an inverting output buffer: when the ip-op output Q is high, Q14 is on and the voltage at the OUTPUT pin (pin 3) is low (close to zero); when the ip-op output Q is low, Q14 is off and the OUTPUT is high (close to VCC ). The output driver is capable of sinking or sourcing current up to about 200mA. The collector of the discharge transistor Q14 is available at the DISCHARGE pin (pin 7). The active-low RESET input (pin 4) to the ip-op can be used to disable the timer operation and ensure that the OUTPUT stays at zero, regardless of the comparator outputs. The dc supply voltage can be between VCC = 5V and VCC = 15V. It should be connected between the VCC (pin 8) and the GROUND (pin 1). With a 5V supply, the output, and the RESET input levels are compatible with standard TTL or CMOS digital logic circuits.

2 Basic Applications
With the addition of an external capacitor and one or two external resistors, the 555 can provide two basic functions: monostable operation, where an output pulse of xed duration is initiated by a short negative pulse on the TRIGGER input, and astable operation, where the timer produces periodic output pulses.

VCC 8 R3 5K THRESHOLD 6 R4 5K
+ + -

RESET 4 C1 R FF S C2 Q 3 OUTPUT

RES Q

CONTROL

TRIGGER DISCHARGE

2 7

R5 5K

555
R8 Q14 100

1 GND
Figure 1: Functional block diagram of the 555 integrated-circuit timer.

2.1 Monostable operation

The circuit connection for the monostable operation is shown in Fig. 2. The corresponding waveforms are shown in Fig. 3. Initially, the TRIGGER input voltage is above the trigger level. Therefore, the ip-op is reset, Q is high, OUTPUT is low, and the discharge transistor Q14 is on. Since Q14 is on, and the DISCHARGE pin is connected to the THRESHOLD input, the capacitor C is discharged. The THRESHOLD voltage is equal to the saturation VCES voltage of the discharge transistor Q14 , which is close to zero. Note that the CONTROL input is left open so that the trigger and the threshold levels are VL = VCC =3 and VH = 2VCC =3. In applications where the CONTROL input is not used, it is a good practice to connect a noise-decoupling capacitor Cd = 10 , 100nF from the CONTROL pin to ground. This provides a low-impedance path for ac noise to ground and ensures that the trigger and the threshold levels stay at the expected dc levels. Note also that the RESET input is high (tied to VCC ) so that the timer operation is enabled. At t = t0 , a short pulse takes the TRIGGER input below the trigger level. This sets the ip-op, the OUTPUT goes high, and the discharge transistor Q14 is turned off. Since Q14 is off, the capacitor C starts to charge up through the resistor R toward VCC . After the interval Tw , the capacitor voltage reaches the threshold level VH = 2VCC =3, the ip-op is reset, the output returns to low, and the discharge transistor Q14 is turned on again. When Q14 is turned on, its collector current quickly discharges the capacitor toward zero, and the circuit is again in the initially assumed steady state. Another short pulse on the TRIGGER 2

VCC 8 R3 5K 6 Trigger pulse Vt 2 Vc C Cd 0.1uF 1 7 Q14 100

+

4 C1 R FF
+ -

RES Q

VH R4 5K VL R5 5K

S C2

Vo

555
R8

Figure 2: Monostable circuit built around the 555 timer. input would be needed to produce another output pulse of duration Tw . Without the external trigger input, the output always stays low, which is why the circuit is called monostable, or one-shot. The basic design specication for a monostable circuit is the output pulse duration Tw . The pulse duration depends on the selection of the external R and C components. Therefore, we would like to determine how Tw depends on R and C . The solution will be found here in more general terms, so that the results can be applied to other similar problems. Consider the R , C circuit in Fig. 4, where at t = 0, the initial capacitor voltage is vc 0 = Vo . For t  0, the circuit is described by the rst-order differential equation:

where V1 is a dc voltage. If we let the capacitor charge (or discharge) completely (for capacitor voltage is vc 1 = V1 . The solution to Eq. 1 is given by1 :

dvc dt

vc RC

V1 ; v 0 = Vo : RC c

(1)

t ! 1), the nal

(2)

vc t = V1 + Vo , V1 e,t= ;

RC :

Now, if we want to know when the capacitor voltage reaches a certain threshold VTH , we can use the solution given by Eq. 2 as follows: vc t = VTH = V1 + Vo , V1 e,t= ; (3)
1

This should be well known ...

>VL TRIGGER Vt(t) OUTPUT Vo(t) 0

<VL close to VCC t VH

CAP VOLTAGE Vc(t) 0

t Tw

Figure 3: Typical waveforms in the monostable circuit with the 555 timer.

R + V1
+ -

C -

Vc(t) Vc(0)=Vo

Figure 4: Capacitor charging (or discharging) circuit.

et=
Therefore,

t=

 V ,V 1 o ln :
VTH , V1

Vo , V1 ; VTH , V1

(4)

(5)

Let us apply the above solution to the problem of nding the output pulse width Tw as a function of the time constant = RC . From Figs. 2 and 3, we have that Vo  0, V1 = VCC , and VTH = VH = 2VCC =3, so that

Tw = ln

,VCC = 2VCC =3 , VCC

ln 3  1:1RC :

(6)

For a specied Tw , Eq. 6 gives only one constraint for R and C . Further constraints, which are less obvious, can nevertheless make a difference between a good and a bad design. Here is a summary of considerations that should be taken into account when selecting the values for R and C : 4

1. When the output is in the low steady-state, the discharge transistor Q14 is on, and we assume that the transistor is saturated so that the voltage at the DISCHARGE and the THRESHOLD pins is VCES  0. The current through the resistor R is then given by:

V , VCES IR = CC R
If

CC  VR :

(7)

R is smaller, IR is higher, and the timer takes more power from the dc supply VCC . Also, if R is too small, the discharge transistor Q14 will come out of saturation, and the voltage at the

DISCHARGE/THRESHOLD pins can be signicantly higher than zero. As a result, in addition to the wasteful power loss, we may have a signicant error in the output pulse width Tw . 2. The input currents to the comparators C 1 and C 2 are small, but not equal to zero. From the data sheets, we read that the threshold input current can be as high as 250nA, and that the trigger input current can be as high as 0:9A. Even worse, the threshold/trigger input current is not a very reliable parameter, because it can vary in a wide range from one device to another. For example, as given in the data sheets, the typical value for the threshold current is only 30nA, although it can be as high as 250nA. In addition, the threshold input current (which is the base current of the internal BJT Q1 (see data sheets), certainly has a very strong temperature dependence, which would further invalidate any design based on the precise knowledge of this current. In the analysis for Tw , we assumed that the threshold input current is zero. In a good design, we should attempt to make the contribution of the threshold current negligible. Therefore, R should be selected so that IR is always much greater than the threshold input current, which gives a maximum R that can be used in the circuit. The condition:

IR
results in

250nA

(8)

For VCC = 10V, we need R 4M .

: (9) 250nA 40M . A practical limit would include a factor of 10, so:

VCC

3. At the end of the output pulse, the discharge transistor Q14 is turned on to discharge the capacitor C toward zero. The discharge is not instantaneous. During the discharge transient, Q14 operates in the IR , which is active region with approximately constant collector current IC . Assuming that IC the case if R was selected properly (see comment 1. above), the discharge takes

tdischarge 

C 2VCC IC 3

(10)

If the discharge time is too long, the timer may not be ready in time to respond to another trigger pulse at the TRIGGER input. 4. Parasitic capacitances on the circuit board and on the inputs to the integrated circuit are usually around 5 , 10pF. These values are not known in advance, may vary from one set-up to another, and from one component to another. Therefore, to avoid errors, the capacitance C should be much greater than the parasitic capacitances.

VCC 8 R3 5K 6
+

4 C1 R FF
+ -

RA

RES Q

VH R4 5K VL

S C2

Vo

RB Vc C Cd 0.1uF

2 7

R5 5K

555
R8 Q14 100 1

Figure 5: Astable circuit (pulse generator) built around the 555 timer.

2.2 Astable operation

With the addition of an external capacitor and two external resistors, the 555 can be congured to produce a periodic pulsating waveform at the output, without any external trigger pulses. The basic conguration for the astable operation is shown in Fig. 5, together with typical steady-state waveforms in Fig. 6. The key difference between the monostable and the astable operation is that the TRIGGER input is connected together with the THRESHOLD input so that the timer triggers itself during operation. The capacitor C is periodically charged and discharged between the trigger level VL = VCC =3 and the threshold level VH = 2VCC =3. Suppose that at t = 0 the output is high, and the discharge transistor Q14 is off. The capacitor is charged through RA and RB until the capacitor voltage reaches VH = 2VCC =3 at t = tH . At this point, the ip-op is reset, the output goes low, and the discharge transistor Q14 is turned on. As a result, C is discharged through RB and the saturated discharge transistor Q14 . At t = tH + tL = Tp , the capacitor voltage drops to VL = VCC =3, the ip-op is set again, the output voltage goes high and the discharge transistor is turned off, starting another period. The times tH and tL can be determined using the same approach used to determine Tw in the monostable circuit. The results are: tL = RB C ln 2  0:693RB C (11)

tH

= RA + RB C

ln 2  0:693RA + RB C

(12)

close to VCC OUTPUT Vo(t) 0 VH CAP VOLTAGE Vc(t) 0 Tp VL t tH tL

Figure 6: Typical waveforms in the astable circuit with the 555 timer. The period of the waveforms is and the frequency is fp
=

Tp = RA + 2RB C ln 2 : t D= H Tp tH RA + RB : RA + 2RB

(13)

1=Tp . The output waveform duty cycle D is:

=

tH + tL

(14)

Since tH

tL , the duty cycle must be greater than 50% in this conguration.

3 Experiment
The experiment has three parts. Unless otherwise noted, use VCC = 15V supply voltage in all experiments. Before you start constructing any circuit on the protoboard, make sure that the DC supply voltage is properly decoupled with an electrolytic capacitor of at least 10 F. Also, your rst step in putting the circuit together on the protoboard should be to connect the DC supply pins (VCC and ground) and to place a ceramic decoupling capacitor of at least 0 :1F between the supply pins. Errors in connecting the supply voltages can easily lead to permanent damages to the ICs. Also, without proper DC voltage decoupling, many seemingly well designed and correctly connected circuits fail to operate properly.

3.1 Monostable circuit design and experimental verication

Design the monostable circuit of Fig. 2 to produce the output pulse of duration Tw = 30s, 2%, for each short trigger pulse. To verify operation of the monostable, generate the trigger pulses from a laboratory pulse generator. If necessary, i.e., if the lab signal generator cannot produce the required trigger pulses, use the circuit you designed in the prelab problem #2. Verify the amplitude, the frequency and the pulse width of the trigger signal before connecting the trigger pulses to the TRIGGER input of the monostable. You must not apply a voltage outside the supply-voltage range (zero to VCC ) to any pin of the 555 ! 7

In the report, show the circuit diagram with labeled component names and values, together with a labeled oscilloscope plot that veries operation of the monostable. Show waveforms of the TRIGGER input, the capacitor voltage, and the OUTPUT. Label the waveforms with signal names, and signicant voltage levels, and time intervals. Measure and record the output pulse duration, and the frequency of the trigger pulses used in the test. Correct the design if the error in the length of the output pulse is more than 2%. Explain what happens if another trigger pulse comes before the end of the output pulse. Show the same scope waveforms as above, and explain the results, if the frequency of the trigger pulses is 50kHz.

3.2 Astable circuit design and experimental verication

Design the astable circuit of Fig. 5 to produce periodic output pulses with frequency fp = 40kHz (2%), and with the width of the LOW output that satises 0:5s tL 1s. In this part, you should observe that the actual fp is signicantly lower that the theoretical value from your paper design. Your task is to investigate and explain the source of the error. Hint: look at the voltage waveform across the capacitor. Why doesnt it oscillate between VL = VCC =3 and VH = 2VCC =3 ? Correct the component values to meet the specications. Show a complete circuit diagram with labeled component names and values. Attach labeled scope waveforms of the capacitor voltage and the output. Measure and record the actual frequency fp and the width tL . Measure and record the actual frequency fp and the width tL for VCC = 10V and VCC = 5V. Can the design meet the specs for the range of supply voltages between 5V and 15V ?

3.3 Design of a touch-tone circuit

It is required to design a circuit where pressing a push-button switch (or touching a jumper wire on the proto-board) produces a 50kHz (5%) tone (square-wave waveform with 50  1% duty ratio, (tH = tL , 1=tH + tL  = 20kHz) that lasts 0:1 (5%) seconds. Show the complete circuit diagram with labeled component names and values. Report the results of experimental verication of your design. Measure the actual tone frequency, the actual duty ratio, and the actual duration of the tone.

4 Prelab Assignment
The prelab assignment is due in the lab on the day when you start working on the experiment. 1. Derive expressions (11) and (12). 2. Suppose a signal generator produces a square-wave signal of 7:5V amplitude, and f = 10kHz frequency, as shown below. Using a resistor, a diode, and a capacitor, and a VCC = 15V DC power supply, design a circuit that would produce output pulses as shown in the gure below. Find the capacitance and the resistance values. This circuit can be used to generate the short trigger pulses required in Section 3.1 of the experiment.
+7.5V from signal generator -7.5V +15V +15+0.7V (approx) t

output

2us (approx) t

0V

3. Design the monostable circuit of Fig. 2 to produce an output pulse of duration Tw for each short trigger pulse, as specied in Section 3.1. Show the circuit diagram with labeled component names and values. Do a PSpice transient simulation to verify the design and attach the simulation results (one page of waveforms). A 555 Spice model is available with the evaluation version of PSpice. This is a paper design for the experimental task described in Section 3.1. 4. Design the astable circuit of Fig. 5 to produce periodic output pulses with frequency fp , and with the width of the LOW output tL = 0:75s, as specied in Section 3.2. Show a complete circuit diagram with labeled component names and values. Do a PSpice transient simulation to verify the design and attach the simulation results (one page of waveforms). This is a paper design for the experimental task described in Section 3.2. 5. Design the touch-tone circuit as specied in Section 3.3. Show a complete circuit diagram with labeled component names and values. Make a copy of your prelab work so that you can use it during the Lab session.