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8 Bit Adder: VHDL Code

This document describes a VHDL code for an 8-bit adder. The code defines an entity called BA_8 that takes in two 8-bit inputs P and Q and outputs their sum in S and carry out in Carry. It instantiates 8 instances of a full adder component FA that are chained together to add the bits from P and Q starting from the least significant bit.

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Manas Ranjan Mantri
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© Attribution Non-Commercial (BY-NC)
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552 views

8 Bit Adder: VHDL Code

This document describes a VHDL code for an 8-bit adder. The code defines an entity called BA_8 that takes in two 8-bit inputs P and Q and outputs their sum in S and carry out in Carry. It instantiates 8 instances of a full adder component FA that are chained together to add the bits from P and Q starting from the least significant bit.

Uploaded by

Manas Ranjan Mantri
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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8 bit adder

Vhdl code
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BA_8 is Port ( P : in STD_LOGIC_VECTOR (7 downto 0); Q : in STD_LOGIC_VECTOR (7 downto 0); S : out STD_LOGIC_VECTOR (7 downto 0); Carry : out STD_LOGIC); end BA_8; architecture Behavioral of BA_8 is Signal K: std_logic_vector(6 downto 0); component FA is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Sum : out STD_LOGIC; Cout : out STD_LOGIC); end component; begin FA1:FA port map(P(0),Q(0),'0',S(0),K(0)); FA2:FA port map(P(1),Q(1),K(0),S(1),K(1)); FA3:FA port map(P(2),Q(2),K(1),S(2),K(2)); FA4:FA port map(P(3),Q(3),K(2),S(3),K(3)); FA5:FA port map(P(4),Q(4),K(3),S(4),K(4)); FA6:FA port map(P(5),Q(5),K(4),S(5),K(5)); FA7:FA port map(P(6),Q(6),K(5),S(6),K(6)); FA8:FA port map(P(7),Q(7),K(6),S(7),Carry); end Behavioral;

RTL SCHEMATIC

TECHNOLOGY SCHEMATIC

TEST BENCH WAVE FORM

SIMULATE BEHAVIORAL MODEL

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