Everand Logo

Welcome to Everand!

  • Discover millions of ebooks, audiobooks, and so much more with a free trial

    From $11.99/month after trial. Cancel anytime.

    A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide
    A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide
    A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide
    Ebook566 pages3 hours

    A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide

    By Veena S. Chakravarthi

    ()

    Read preview

    About this ebook

    This book provides a comprehensive overview of the VLSI design process. It covers end-to-end system on chip (SoC) design, including design methodology, the design environment, tools, choice of design components, handoff procedures, and design infrastructure needs. The book also offers critical guidance on the latest UPF-based low power design flow issues for deep submicron SOC designs, which will prepare readers for the challenges of working at the nanotechnology scale. This practical guide will provide engineers who aspire to be VLSI designers with the techniques and tools of the trade, and will also be a valuable professional reference for those already working in VLSI design and verification with a focus on complex SoC designs.

    • A comprehensive practical guide for VLSI designers;
    • Covers end-to-end VLSI SoC design flow;
    • Includes source code, case studies, and application examples.

    LanguageEnglish
    PublisherSpringer
    Release dateSep 25, 2019
    ISBN9783030230494
    A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide

    Related to A Practical Approach to VLSI System on Chip (SoC) Design

    Related ebooks

    Electrical Engineering & Electronics For You

    View More
    View More

    Related podcast episodes

    Related categories

    Reviews for A Practical Approach to VLSI System on Chip (SoC) Design

    0 ratings

    0 ratings0 reviews

    What did you think?

    Tap to rate

    Review must be at least 10 words

      Book preview

      A Practical Approach to VLSI System on Chip (SoC) Design - Veena S. Chakravarthi

      © Springer Nature Switzerland AG 2020

      V. S. ChakravarthiA Practical Approach to VLSI System on Chip (SoC) Designhttps://doi.org/10.1007/978-3-030-23049-4_1

      1. Introduction

      Veena S. Chakravarthi¹  

      (1)

      Sensesemi Technologies Private Limited, Bangalore, India

      Veena S. Chakravarthi

      Keywords

      VLSICMOS technologySOCIP coresEDA toolsDesign goalsMoore’s lawHigh K materialDie size

      1.1 Introduction to VLSI

      VLSI is an acronym for very large-scale integration, which enables integration of hundreds of millions of transistors on a small silicon chip of a few square millimeter size. This technology is solely responsible for the small sizes of heavily loaded capabilities of the electronic gadgets and gizmos of today, ranging from any type of mobile phone to smart consumer infotainment product, to smart servers, to household electronic devices. The dominant VLSI technology being CMOS technology follows the famous Moore’s law the number of transistors in a chip doubles every 18 months which is proven correct since it was stated in 1965. However, this growth in density of transistors posed and continues to pose innumerable challenges to the designers who are required to upgrade their skills constantly to address them.

      1.2 Application Areas of SOC

      System on chip (SOC) has become an indispensable part of many products in almost all domains. There are SOCs being deployed traditionally in communications, data storage, and high-tech computing domains since VLSI days, and with high-level integration including analog, sensor technologies, low-power capabilities, and high signal processing possibilities, SOC is penetrating into domains like medical, automotive, security, and defense.

      1.3 Trends in VLSI

      The trends in growth of VLSI technology can be classified under the following heads:

      Complexity

      Speed of operation

      Die size

      Design methodology

      1.3.1 Complexity

      Since the time, transistors were invented; for over the past five decades now, physical dimension of the transistor is constantly shrinking. This has resulted in packing more and more transistors on a silicon wafer integrating more and more functionalities into the circuits. This phenomenon called scaling is still continuing. But, it is said that in the next 2 to 3 years, scaling of transistor’s dimensions will reach a point where it will be so expensive that it becomes commercially not viable to scale down further. However, all these years the predicted demise of the Moore’s law has been repeatedly proven wrong. Even today there are many other technologies beyond CMOS technologies, which appear promising in offering alternate solutions in continuing the everlasting thirst for more and more functionality in devices of reduced form factor. It is the scaling, however, which is responsible for the tremendous growth in computing and communication power of the processors which has changed the way we sense, process, store, display, and communicate information of any magnitude. Over the past five to six decades, chips have accommodated circuits, which are time critical to the entire system. Today’s electronic gadgets house very few components and a few interface peripherals, apart from the system on chip (SOC) and unlike the large systems of yesteryears. The trend in integrating more and more circuits to form SOC was the result of advancement in allied technologies like photolithography, fully depleted wafer technologies, high K materials, 3D stacked silicon wafer technologies, etc. This was supported by the enhancements in EDA tools and enhancing algorithms, which run in them. As per Wikipedia [1], as of 2017, the largest transistor count in a commercially available single-chip processor is 19.2 billion – AMD’s Ryzen-based Epyc. In other types of ICs, such as field-programmable gate arrays (FPGAs), Xilinx’s Everest/Versal [2] has the largest transistor count, containing around 50 billion transistors showing the complexity of the SOCs of current days.

      1.3.2 VLSI Circuit to System on Chip

      VLSI in the 1970s were small-time critical circuits and were required to work with standard general-purpose processors to realize integration on printed circuit boards (PCBs) . These time critical circuit designs were entered manually as schematics as, it was for PCB designs where, the transistors and passives components like resistors and capacitors were manually interconnected to form the VLSI circuit. The advancement in CMOS technologies, packing more and more transistors in a small area, and the invention of automated synthesis tool (converts the design representation using hardware description language into schematic) made it possible to define large complex designs for complete systems. Scaling phenomenon and advancement in process & custom design methodologies have enhanced the compatibility of non-digital circuit fabrication to CMOS fabrication, thus, enabling the integration of non-digital components into packages containing IC (technology called system in package (SIP)) or on to chip as system on chip (called SOC). Non-digital components, also called analog and mixed signal components include RF, analog, and sensor devices. The International Technology Roadmap for Semiconductors (ITRS) [3] trend showing integration of digital and non-digital components into single chip is shown in Fig. 1.1.

      ../images/479033_1_En_1_Chapter/479033_1_En_1_Fig1_HTML.png

      Fig. 1.1

      ITRS trend showing the integrating digital and non-digital components in single chip shown as dual trend in the International Technology Roadmap for Semiconductors: miniaturization of the digital functions (More Moore) and functional diversification (More-than-Moore). (Source: ITRS white paper)

      The International Technology Roadmap for Semiconductors (ITRS) has emphasized that scaling in CMOS technology and its associated benefits in terms of performances will continue. This direction for further progress is labelled More Moore. The second trend is integrating non-digital functionalities which do contribute to the miniaturization of electronic systems , although they do not necessarily scale at the same rate as the digital functionality. This trend is named More-than-Moore (MtM).

      Advances in EDA tools made it possible to realize complete systems on chip by means of automation and analysis capability. SOC modelled with its behavioral description in hardware description language (HDL) is converted to the design netlist corresponding to schematics by the process called synthesis, and further, the design process called physical design was able to generate the design database, (this database is in GDS II format and the process of submitting the database to the fab is called tape-out) which is used directly in the fabrication process of chip. In the present day, VLSI designs are all system on chip designs of large complexity. The complexity of the SOC chips range from simple microcontroller systems to large network on chips utilizing hundreds of millions of transistors. Figure 1.2 shows the evolution from a simple circuit on chip to system on chip (SOC).

      ../images/479033_1_En_1_Chapter/479033_1_En_1_Fig2_HTML.png

      Fig. 1.2

      Complexity trend in ICs. (Source: Wikipedia; figures licensed under GFDL)

      Today’s SOCs, for example, smartphone SOC like QUALCOMM’s snapdragon series, contain ARMv8 processor, general-purpose processor, DSP, RF transceiver, WLAN 802.11 ac cores, embedded memories, cache, and analog interfaces embedded in chip. Also, each of the functional cores in SOC, like WLAN 802.11 ac core and RF transceiver, is controlled by one or more embedded processors of various complexities. Another example is Intel’s i-series chips which contain multiple processor cores , which can function independently, and fast interface cores complying to interface standards like PCI-Express, USB, and on-chip memories.

      1.3.3 Speed of Operation

      Another trend observed over in the last six decades is the phenomenal increase in speed of operation of the systems. Figure 1.3 shows the trends in speed, power, transistor density, and number of logic cores. High-speed system on chips (SOCs) developed by leading semiconductor companies claim to operate at a frequency of 2.5 to 3 Ghz. Also, few of the system on chips support the data transfer rate of 100 Gbps. All these trends, offered many challenges to the designers, and this resulted in changes in design methodology over the years. The challenges offered by this trend are responsible for devising new design methods and modelling done at the high level of design abstraction and design reuse.  

      ../images/479033_1_En_1_Chapter/479033_1_En_1_Fig3_HTML.png

      Fig. 1.3

      Complexity trends in computation system on chip

      1.3.4 Die Size

      As the transistor size decreased, more and more transistors were packed in smaller area on a silicon die; thus the transistor density (number of transistor per unit area of silicon) increased. This resulted in realizing more and more functions in a small area of the die and enabled realization of complete coordinated functions of the system to be designed on the die. Coping with the Moore’s law prediction, die size increased 14% every 2 years (Source: Intel), thus abling to realize a complete system on a chip (SOC). Thus, began the era of miniaturization which resulted in generations of computers from main frames to personal computers of high performances. Figure 1.4 shows three generations of computers [4] made by system on chips (SOCs).

      ../images/479033_1_En_1_Chapter/479033_1_En_1_Fig4_HTML.jpg

      Fig. 1.4

      Generations of computers. (Source: IBM)

      Today’s high-performance gadgets and gizmos, smart handheld and portable devices, which can be carried in pockets are the results of this miniaturization and integration of large number of functional blocks using VLSI technology.

      1.3.5 Design Methodology

      To complement the advancements in VLSI technologies over the past six decades, the design methodology has evolved over the years. This was possible by the availability of large computing resources and the development of design automation tools. These tools can be considered as linchpin technologies, which are major enabler for complex SOC design. The examples are synthesis tool, simulators, static timing analysis (STA) tool, and physical design tools. Figure 1.5 depicts the EDA tools complementing the technological growth by computerized automatic methods in the place of hand designs. Further, the design productivity gap instigated the virtual design core developments and made reuse an inevitable choice in the large designs of today. During this time the design entry methods changed from simple schematic entry to interconnection of many functional design cores of processors and peripherals called intellectual property cores-(IP cores). The intellectual property core is a functional block which can be designed newly or bought on licensing terms or royalty terms from third party design companies. Once bought, it can be reused multiple times. The number of intellectual property (IP) cores being integrated is close to hundred and more in present-day systems. Enabler to this advancement is also the high computation capable workstations/systems, which enabled processing and storage of large database using design and verification automation tools possible.

      ../images/479033_1_En_1_Chapter/479033_1_En_1_Fig5_HTML.png

      Fig. 1.5

      EDA tools complementing the technological advancements

      The choice of design methodology for a SOC depends on conflicting factors: performance in terms of speed or power consumption, cost, and volume. Major design options are custom design, standard cell-based design, and the array-based design. A complex SOC design may employ any or all these options as a methodology.

      1.4 SOC Design and Development

      With the changing technology , the design and development environment is constantly upgrading with newer advanced skill sets; intelligent tools with advanced algorithms; standard design guidelines resulting in more predictable chip performance; modelling and hardware description languages; high-capacity development systems operating at high frequency of the order of tens of GHz; large memories of the order of multiples of terabytes; and processing power with multiples of parallel RISC, graphic and DSP processor cores, and high-end graphic displays. This demanded human resources with newer skill set.

      1.5 Skill Set Required

      As the design complexity and methodology changed over the past couple of decades with advent of intelligent EDA tools, the skill set required in the VLSI designer changed from circuit fundamentals to ability in realizing the functionalities by logic definitions and modelling using hardware description languages. Major hardware description languages used to describe the hardware functions are Verilog and VHDL. This should be supported by the knowledge of the tool usage to get the desired functionality by guiding the tools by proper input of the design description files and constraints. It is important for the designer to have fundamental knowledge of chip design with design flow. Knowing one of the scripting languages like Tcl-Tk, Perl will come in handy in automating the simulation, synthesis, and STA scripts which are to be run iteratively and when reports and logs generated by design tools are to be analyzed. Most importantly, imagining the hardware and then coding its intended behavior help in hardware realization and debug. Flexibility to work in any department of design like logic design, synthesis, timing analysis, and physical design and FPGA validation make a designer most desirable.

      1.6 EDA Environment

      As the design complexity evolved from time critical circuitry to system on chip, the algorithm-based tools for synthesis, timing analysis, and physical design tools like placement and routing got developed and matured to the extent that the tools were able to write out design database for most advanced fabrication technology. The design database is used to make masks based on advanced optical and electron beam lithography and used in chip fabrication process. In parallel, the verification methodologies like UVM, Electronic design automation (EDA) tools like Genus, Design Compiler, RTL Compiler, NCSim, Questa Sim, and VCS; and system verification framework and languages like Vera and SystemVerilog were developed which proved first time success of the fabricated system chips with great correlation to pre-processed simulations or validations. Important design automation and process tools in the EDA environment of SOC design are (1) simulators, (2) synthesis tool, (3) static timing analyzer, (4) P & R tools, parasitic extractor, electrical rule checker, and design rule check. The FPGA-based developments which were initially seen as a competition to VLSI development started to be seen as complementing the VLSI design process for first time success of the

      Enjoying the preview?
      Page 1 of 1