ASIC Design and Synthesis: RTL Design Using Verilog

© Springer Nature Singapore Pte Ltd. 2021

V. TaraateASIC Design and Synthesis https://doi.org/10.1007/978-981-33-4642-0_1

1. Introduction

Vaibbhav Taraate¹  

(1)

1 Rupee S T, Pune, Maharashtra, India

Vaibbhav Taraate

Email: [email protected]

Keywords

ASICFPGASemi-customFull customProgrammable logic deviceHDLVerilogVHDLSystemVerilog

ASIC is an application specific integrated circuit and designed for specific application.

If we recall the beginning of the miniaturization era, then we can imagine the basic bipolar junction transistor invention at Bell Labs (now AT&T) during year 1947. The first bipolar junction transistor was invented by William Shockley, Bardeen, and Brattain at Bell Labs and got the Nobel Prize in physics during the year 1956. The first integrated circuit was introduced by the 26-year-old engineer Jack Kilby at Texas Instruments (TI).

The popularity of CMOS devices increased during the year 1963 due to low power, high package density, and high-speed requirements.

During the year 1965-1975, Gordon Moore stated Moore’s law that is ‘Number of transistors in dense integrated circuit doubles in approximate 18–24 months.’ The observation of Gordon Moore was valid till the year 2015. It may require modification for the technology node below 10 nm. According to my observation to double the transistors, it may require almost 36 months which may be true during next few decades.

To have basic understanding of the ASIC design and flow, the objective of the remaining sections is to get familiarity with the types of ASICs, different abstraction levels, and few examples which can be useful to think about the ASIC design and strategies.

1.1 ASIC Design

The era of miniaturization from the year 1960 to 2020 has witnessed lot of the evolutions and design changes. What we need to understand is that, what is exactly ASIC design? Now consider the small square of few micrometers or nanometer which is empty box. Now for the specific functionality, design team will fill this empty box with functional blocks. The design team which performs this is front-end (logic) design team.

The backend or physical design team works in the area of floor planning to physical verification at the chip level for the specific technology node.

The manufacturing unit which is foundry performs the manufacturing and packaging of the chip in mass, and initially few sample pieces will be tested by the design houses to understand the intended design outcome.

Now how all above is achieved? All the design-related work is achieved by the intelligent chip designers working in the various areas of the chip design using the Electronic Design and Automation (EDA) tools. The various popular EDA tools are from Synopsys and Cadence and extensively used in the design of chip and to improve or to achieve the desired performance.

With the functionality of the chip, it requires to understand about the constraints such as area, speed, and power and the main goal of the logic design and physical design team is to understand the block-level and top-level constraints and to have the better strategy to achieve the desired performance.

For the basic understanding, consider the pipelined processor which performs the basic arithmetic and logic operations such as addition, subtraction, multiplication, division, XOR, OR, AND, and NOT. What we need to imagine at the higher level is the functional blocks, complexity of the design that is rough estimation of the area, what constraints we should apply, and what exactly we will achieve. At the beginning, we will have just the basic idea of the blocks and as the design evolves we will land up into the phase of the chip architect.

For the idea of the architecture of the above chip, the basic layout is shown in Fig. 1.1. The subsequent chapter discusses the design flow, chip architecture, micro-architecture!

Fig. 1.1

Basic chip layout

1.2 Types of ASIC

ASIC Design: ASIC stands for the application-specific integrated circuit and is designed to perform the specific application. For example, the processor or controller is used to process the specific information.

The following are different types of ASICs

1.

Full-custom ASIC

2.

Semi-custom ASIC

3.

Gate array-based designs

4.

Structured ASICs.

Full-Custom ASIC: In this type of ASICs, the design starts from scratch for the specific technology node. Each cell is designed depending on the technology node requirements. This approach is useful for high volume production, and one can imagine the microprocessors and floating-point processors, which are required in the design and can be designed using the full-custom design flow.

The major advantage of the full-custom design is that for the high volume production it gives the lower power, high speed, and the least gate count. Achieving the constraints of the speed, area, and power is time consuming for this flow. But as the cells are designed from the scratch for the desired technology nodes, the desired constraints can be achieved.

The major disadvantage of this flow is the high non-recurring expenditure and the long design cycle time.

Standard Cell-Based ASICs

In this type of design flow, the standard library cells such as NAND, NOR, XOR, and flip-flops are used during the design. The beauty of this flow is that it uses the pre-defined and prefabricated cells, for example, RAM hard macro-cores, etc. The transistors and interconnects are customized; that is, all the mask layers are customized.

The advantage of this flow is that, as compared to full-custom ASIC the design cycle time is shorter and for the specific technology node the pre-validated standard cells like microprocessors and macros are available during the design.

The disadvantage is that as compare to the gate array based ASICs, the design has the high NRE and it needs separate fabrication mask for each design.

Gate Array-Based ASIC

In this type of ASICs, the wafers are prefabricated with unconnected gate array. That is, wafers are common for all the designs. The types of gate array-based ASICs are mainly of following two types.

1.

Channeled gate array

2.

Channel-less gate array.

Channeled Gate Array: In this type of ASIC, the interconnects use the pre-defined spaces between the rows of base cells.

Channel-Less Gate Array: In this type of ASICs, the few top mask layers are customized.

The major advantage of the gate array-based ASIC is that, lower NRE cost as the same wafer is fabricated for the multiple designs. Another main advantage is the low turnaround time.

The main disadvantages are the low density, lower volume, and the less optimized design.

Structured ASICs

A structured ASIC falls between and gate array and a standard cell-based ASIC.

The main design task involves mapping the design into a library of building block cells and interconnecting them as necessary. The main important points regarding the structured ASICs are components are ‘almost’ connected in a variety of pre-defined configurations and only a few metal layers are needed for fabrication which in turn drastically reduces turnaround time.

The advantages of the structured ASIC are low NRE cost, less complexity, low power consumption, high performance, and the smaller marketing time.

The main disadvantage is that the team needs to have better understanding of the design constraints due to the use of prefabricated design cells.

1.3 Abstraction Levels

The design can go through the different abstraction levels such as functional design, logic design, gate-level design, and the switch-level design. This section discusses these abstraction levels in more detail.

1.

Functional Design: Now imagine a scenario to design a product or chip, so the first thought is the product idea or/and depending on the idea the chip functionality can be extracted. The functional design is basically the outcome of the functional specification, and the group of team members can create the high-level and low-level design document and can code the functionality using the higher-level language such as C or C++. For example, consider the H.264 encoder design, and the functional design team can create the golden reference model using the high-level language by using the following

(a)

The types of frames which need to be processed

(b)

The frame support

(c)

The prediction blocks and functionality

(d)

The quantization and transform algorithms required

(e)

The entropy coding methods

If the desired functionality is validated, then the design can be considered as golden reference model which can be used throughout the design.

2.

LogicDesign: The logic design team understands the architecture of the chip and the partitioning mechanisms to complete the RTL design, where RTL stands for the register transfer level. The team of professionals uses the HDL such as VHDL, Verilog, and SystemVerilog to have the RTL design and verification at the block and top level. The main advantages of the HDL used during the RTL design are as follows:

(a)

The HDL supports the concurrent and sequential constructs.

(b)

HDL supports the notion of time.

(c)

HDL supports describing the interfaces and ports as input, output, bidirectional.

(d)

HDL supports the edge- and level-sensitive design constructs.

For more details about the RTL design and verification, refer Chaps. 3 and 4. The logic design flow is discussed in Chap. 2.

The RTL design example using the Verilog to infer the 2-bit shift register using the non-blocking assignment is described in Example 1.

Example 1

The RTL description using Verilog

3.

Gate-Level Design: The RTL is given as one of the inputs to synthesis tool to get the gate-level netlist. The synthesis is process of getting the lower level of abstraction from the higher-level design (Fig. 1.2).

Fig. 1.2

RTL schematic of Example 1

4.

Switch-Level Design: The design using the CMOS standard cells and switches is called as switch-level design. In the simple term, the physical design or backend design is like playing with the switches and standard cells, macros for the specific technology node. The backend/physical design flow is discussed in Chap. 2.

1.4 Design Examples

Now consider the ASIC design of H.264 encoder and decoder, and what we should do?

1.

Market survey to understand the availability of various products in the market

2.

The functional specification of the H.264 encoder and decoder

3.

The functional design documentation such as high-level design (HLD)and low-level design (LLD) and design planning

4.

Logic Design: Plan the design

(a)

Specification understanding and the architecture design

(b)

RTL design and verification

(c)

Synthesis/DFT and timing verification

5.

Physical Design: Design from floor planning to physical verification

(a)

Planning of the design (floor planning and power planning)

(b)

CTS

(c)

Place and route

(d)

Physical and timing verification

(e)

GDSII

6.

Manufacturing and Test: The design manufacturing and test phases

(a)

Fabrication

(b)

Packaging

(c)

Test.

Consider the initial floor plan of the H.264 encoder (Fig. 1.3).

Fig. 1.3

Initial floor plan of H.264 encoder

1.5 What We Should Know?

During the ASIC design cycle with functional design and validation, we should focus on the area, speed, and power constraints.

1.

Area: The chip area and the logic area which defines the overall density of the design in the few micrometer square. Meeting the area constraints is one of the important tasks during the logic and physical synthesis. The area optimization can be achieved at various levels such as

(a)

Architecture tweaks

(b)

RTL tweaks

(c)

Using synthesis commands

(d)

At the physical design using dedicated cells

2.

Speed: The speed is another important constraint and can be achieved at the block and top level using the

(a)

Synopsys PT commands

(b)

RTL tweaks

(c)

Architecture tweaks

(d)

During physical design

(e)

Using the dedicated IPs

3.

Power: The power, static and dynamic are another important constraints for ASIC and can be achieved using the following

(a)

Use of low-power architecture

(b)

Low power cells

(c)

RTL tweaks to reduce the dynamic power

(d)

Low power format

4.

Clock Skew: The skew is the difference between the clock arrivals at two different coordinates.

(a)

Positive Clock Skew: The launch flip-flop is triggered first and then capture flip-flop.

(b)

Negative Clock Skew: The launch flip-flop is triggered last, and capture flip-flop is triggered first.

5.

Slack: The slack is the difference between the two different time instances.

(a)

Setup Slack: The setup slack is the difference between the data required time and data arrival time.

(b)

Hold Slack: The hold slack is the difference between the data arrival time and data required time.

6.

Clock Gating: The use of the clock gating cells to minimize the dynamic power.

7.

Synchronous Design: All the flip-flops in the design are triggered by using the common clock source.

8.

Asynchronous Design: The flip-flops in design are triggered by the different clock sources.

1.6 Important Terms Used Throughout Design Cycle

The following are few important terms which we should know during the ASIC design cycle.

1.

Architecture: Block-level representation of design

2.

Micro-architecture: Sub-block-level representation of design

3.

RTL: Register transfer level

4.

RTL design: Design using the HDL synthesizable constructs

5.

RTL verification: The testbench and automation using the non-synthesizable constructs

6.

Synthesis: The process of getting the gate-level netlist from the RTL. Or it is the process of getting the lower level of abstraction from the higher-level design

7.

DFT: Design for test to find the manufacturing defects

8.

STA: Static timing analysis at the pre-layout or post-layout

9.

Floor planning: The chip floor plan

10.

Power planning: The power mesh and ring planning for the chip

11.

CTS: Clock tree synthesis, the clock trees for uniform distribution of skew, and the strategy

12.

P and R: Placement and routing that is the placement of standard cells and macros, IPs, and to route them

13.

Physical verification: The verification that is LVS and DRC

14.

LVS: Layout versus schematic check

15.

DRC: Design rule check

16.

Back annotation: The RC extraction

17.

GDSII: GDSII stream format, common acronym GDSII, is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork.

1.7 Chapter Summary

The following are few important points to conclude the chapter.

1.

‘Number of transistors in dense integrated circuit doubles in approximate 18–24 months’ is called as Moore’s law.

2.

ASIC stands for the application-specific integrated circuit.

3.

FPGA stands for the field programmable gate array.

4.

The major advantage of the full-custom design is that for the high volume production it gives the lower power, high speed, and the least gate count.

5.

The main advantage of the semi-custom ASIC is, as compared to full-custom ASIC the design cycle time is shorter and for the specific technology node the pre-validated standard cells like microprocessors and macros are available during the design.

6.

The major advantage of the gate array-based ASIC is that lower NRE cost as the same wafer is fabricated for the multiple designs.

7.

The main design constraints are area, speed, and power.

© Springer Nature Singapore Pte Ltd. 2021

V. TaraateASIC Design and Synthesis https://doi.org/10.1007/978-981-33-4642-0_2

2. ASIC Design Flow

Vaibbhav Taraate¹  

(1)

1 Rupee S T, Pune, Maharashtra, India

Vaibbhav Taraate

Email: [email protected]

Keywords

ASICLogical designPhysical designProgrammable ASICsFPGASynthesisRTL designVerificationDFTLVSDRCSTAFloor planningPower planningCTSPlace and routePhysical verificationGDSII

Understanding of the ASIC design flow plays an important role during design cycle.

As discussed in the previous chapter, the ASICs can be of type full-custom, semi-custom, gate array-based ASICs. The major objective of the following few sections is to have the detailed discussion about the semi-custom ASIC design flow and the programmable ASIC design flow. The important design examples are also discussed in the next few sections and useful during the ASIC and FPGA design.

2.1 ASIC Design Flow

The semi-custom ASIC design in which the standard cells and macros which are pre-validated is used. As discussed in Chap. 1, we can have different types of ASICs such as full-custom, semi-custom, gate array-based and depending on the design requirements we can choose one of the flows. Figure 2.1 describes few of the important design phases during the ASIC design cycle.

Fig. 2.1

Semi-custom ASIC design flow

1.

Market Survey and Specification Extraction: It is one of the important phases during the design cycle. Before the logic design, the team performs the market survey to understand what are the different products of similar type available in the market. Origin of any design idea or product can be realized in the quick time, and product should be excellent in all the aspects that are the major objective of any organization. The excellence in the design and product innovation is objective of many research and development organizations. For example, consider Intel as processor design organization, what they work on the processing capability, low power architecture design, high-speed designs, signal integrity, and more reliability to their chipsets.

For new idea, finalization of the specification and the architecture of the chip is the primary task and for that the market survey plays an important role. Following the team does during the market survey.

(a)

The detailed understanding of the available products

(i)

Understanding of functionality, speed, power, and area

(ii)

Understanding about the electrical characteristics

(iii)

Understanding about the mechanical assembly and packaging

(iv)

Understanding about the user interfaces

(b)

The volume and cost of product

(c)

End customer base

(d)

How the new idea can be better as compared to existing products?

The main outcome of all above is to extract the specifications of the product or chip at various levels. Our goal is to work on the functional design of the chip so we will consider the functional specifications.

Let us consider the 32-bit processor what we need is the following!

(a)

The operations performed by the processor such as arithmetic, logical, data transfer, branching, and floating point

(b)

The complexity of bus interfaces such as address bus and data bus

(c)

The performance improvement mechanism such as pipelining and the configuration support

(d)

The electrical characteristics of interfaces such as slew, voltage levels, and power

(e)

The external interface information and compatibility

(f)

The internal storage information and the data computation schemes

(g)

The IP availability and their