Semiconductor Manufacturing

This research is motivated by issues faced by a large manufacturer of semiconductor devices. Semiconductor manufacturing companies allocate millions of dollars every year for new types of machine tools for their facilities. Typically these are special purpose machine tools which are made to order. The rate of change in products and technology makes it diÅcult for manufacturers to have a

Due to increased competition, semiconductor manufacturing has received considerable research attention over the last few decades. As a result, several optimisation and heuristic solution procedures are available to solve a variety of operational planning and control ...

When computing production plans and available-to-promise statements, the randomness of flow times and yield rates are the two major sources of uncertainty. Considering both of these uncertainties, this study employs a simple formula for computing the standard deviation for cumulative good product output of a particular product type at a particular time. Using this standard deviation, the necessary safety stock for that product type at that time can be obtained. This study was motivated by semiconductor wafer manufacturing, which requires many process steps performed by highly unreliable equipment. Such an environment causes the means and the variances in flow times to be generally larger than those for other industries. It also makes yield rates uncertain. Thus, when making order quotations and calculating production plans, safety stocks must be used to guard against the uncertainties of the manufacturing processes to ensure on-time-delivery ratios and to provide better customer service.

In today's tight, competitive, and volatile market in semiconductor manufacturing, a successful semiconductor manufacturer has to look into multiple performance indices such as cycle time and on-time delivery. Effective dispatching mechanism is a widely used strategy to achieve these performance indices simultaneously. In the past, dispatching studies in semiconductor manufacturing have primarily focused on the level of tool dispatching. This

An overview of a variety of examples that deploy intelligent manipulation of controllable magnetic fields is presented. Magnetic Field Assisted Assembly is described in detail as a future scalable manufacturing process for semiconductor device integration with significant improvement in yield and reduction in costs. Magnetic field augmented rotational system is presented as a future approach to energy needs in a number of situations. The proposed examples address applications in key areas of the economy including energy, healthcare, manufacturing and materials.

Semiconductor fabrication facilities (fabs) continue to expand in both complexity and volume. As a result, integrated models are required to determine even high level impacts to key success indicators. In order to gain insight into how the components of a factory impact performance metrics, Intel uses an integrated discrete-event simulation modeling approach. Two models, one fab capacity and one automation model, are used. This paper discusses the methodology for building and integrating both models, and the results from using this method.Both the fab capacity and automation models have a variety of input parameters that are required to drive the simulation. In addition, each model produces output parameters, some of which are used as inputs to the other model. An iterative feedback technique eventually results in a convergence on the appropriate data to feed the fab capacity model, which enables Intel to determine the impact of automation on 300mm wafer semiconductor manufacturing,...

Resource consumption directly impacts the cost of semiconductor manufacturing and indirectly contributes to environmental pollution. Several resource conservation projects and surveys since 1996, have been performed at Sematech member companies and suppliers demonstrating significant reductions in tool and resource consumption are possible but are they enough? The ITRS roadmap continues to challenge new fabs to meet ever-decreasing energy goals. The World Semiconductor Council and SEMI have issued their white paper on energy suggesting normalized energy reductions for wafer fabs. In order to achieve measurable reductions both factory owners and tools suppliers need to baseline their energy consumption and establish specific targets for improvement

Accompanying the unceasing progress of integrated circuit manufacturing technology, the mainstream production mode of current semiconductor wafer fabrication is featured with multi-variety, small batch, and individual customization, which poses a huge challenge to the scheduling of cluster tools with single-wafer-type fabrication. Concurrent processing multiple wafer types in cluster tools, as a novel production pattern, has drawn increasing attention from industry to academia, whereas the corresponding research remains insufficient. This paper investigates the scheduling problems of dual-arm cluster tools with multiple wafer types and residency time constraints. To pursue an easy-to-implement cyclic operation under diverse flow patterns, we develop a novel robot activity strategy called multiplex swap sequence. In the light of the virtual module technology, the workloads that stem from bottleneck process steps and asymmetrical process configuration are balanced satisfactorily. Moreover, several sufficient and necessary conditions with closed-form expressions are obtained for checking the system’s schedulability. Finally, efficient algorithms with polynomial complexity are developed to find the periodic scheduling, and its practicability and availability are demonstrated by the offered illustrative examples.

The constant increase of the capital needed for a semiconductor facility has brought a huge interest in two methodologies: Theory of Constraints (TOC) and Total Productive Maintenance (TPM) which have been shown to be adequate in optimizing the return on capital equipment. This article shows that both methodologies are convergent. The appropriate use of both together can make it possible to maintain productivity improvement rates in the semiconductor business. The Overall Equipment Efficiency (OEE) measurements are the driver metrics for an effective TPM program. OEE measurements are easy to obtain, nevertheless, the analysis of these parameters requires a large amount of accurate data that are difficult to obtain in a production environment. In addition, it needs the dedication of a considerable amount of effort and human resources to improve in all the organizations (production, maintenance, engineering, etc.). It is widely accepted that bottlenecks should be entered in a TPM program, but for non-bottlenecks, it is not easy to determine which machines should enter the program, their target and their impact on the global fab efficiency. In this study we present a systematic method of approaching this problem

Slot die coating is growing in popularity because it is a low operational cost and easily scaled processing technique for depositing thin and uniform films rapidly, while minimizing material waste. The complex inner geometry of conventional slot dies require expensive machining that limits accessibility and experimentation. In order to overcome these issues this study follows an open hardware approach, which uses an open source 3-D printer to both fabricate the slot die and then to functionalize a 3-D slot die printing system. Polymer materials are tested and selected for compatibility with common solvents and used to fabricate a custom slot die head. This slot die is then integrated into a 3-D printer augmented with a syringe pump to form an additive manufacturing platform for thin film semiconductor devices. The full design of the slot die system is disclosed here using an open source license including software and operational protocols. This study demonstrates that functional lab-grade slot dies may be 3-D printed using low-cost open source hardware methods. A case study using NiO2 found an RMS value 0.486 nm, thickness of 17 to 49nm, and a maximum optical transmission of 99.1%, which shows this additive manufacturing approach to slot die depositions as well of fabrication is capable of producing viable layers of advanced electronic materials. Using this method, a cost savings of over 17,000% was obtained when compared to commercial slot die systems for laboratories.

Plasma processes can present difficult control challenges due to time-varying dynamics and a lack of relevant and/or regular measurements. Virtual metrology (VM) is the use of mathematical models with accessible measurements from an operating process to estimate variables of interest. This thesis addresses the challenge of virtual metrology for plasma processes, with a particular focus on semiconductor plasma etch. Introductory material covering the essentials of plasma physics, plasma etching, plasma measurement techniques, and black-box modelling techniques is first presented for readers not familiar with these subjects. A comprehensive literature review is then completed to detail the state of the art in modelling and VM research for plasma etch processes.

To demonstrate the versatility of VM, a temperature monitoring system utilising a state-space model and Luenberger observer is designed for the variable specific impulse magnetoplasma rocket (VASIMR) engine, a plasma-based space propulsion system. The temperature monitoring system uses optical emission spectroscopy (OES) measurements from the VASIMR engine plasma to correct temperature estimates in the presence of
modelling error and inaccurate initial conditions. Temperature estimates within 2% of the real values are achieved using this scheme.

An extensive examination of the implementation of a wafer-to-wafer VM scheme to estimate plasma etch rate for an industrial plasma etch process is presented. The VM models estimate etch rate using measurements from the processing tool and a plasma impedance monitor (PIM). A selection of modelling techniques are considered for VM modelling, and Gaussian process regression (GPR) is applied for the first time for VM
of plasma etch rate. Models with global and local scope are compared, and modelling schemes that attempt to cater for the etch process dynamics are proposed. GPR-based windowed models produce the most accurate estimates, achieving mean absolute percentage errors (MAPEs) of approximately 1.15%. The consistency of the results presented suggests that this level of accuracy represents the best accuracy achievable for
the plasma etch system at the current frequency of metrology.

Finally, a real-time VM and model predictive control (MPC) scheme for control of plasma electron density in an industrial etch chamber is designed and tested. The VM scheme uses PIM measurements to estimate electron density in real time. A predictive functional control (PFC) scheme is implemented to cater for a time delay in the VM system. The controller achieves time constants of less than one second, no overshoot, and excellent disturbance rejection properties. The PFC scheme is further expanded by adapting the internal model in the controller in real time in response to changes in the process operating point.

In this paper, next-generation lithography (NGL) for the 22 and 16 nm technology nodes and beyond is reviewed. A broad range of topics, including history, technologies, critical challenges, and the most plausible candidates are discussed. The 22 and 16 nm technology nodes rely on NGL. NGLs have been extensively studied. Because of technological issues, the semiconductor industry has stopped pursuing several NGLs, such as X-ray proximity lithography, ion projection lithography, and scattering with angular limitation projection electron lithography. Currently, the primary candidate technologies are extreme ultraviolet lithography (EUVL), maskless lithography (ML2), and nanoimprint lithography (NIL), with EUVL being the leading candidate. Since EUVL was first proposed in 1988, many studies have been conducted. Currently, there is no “show stopper” for EUVL. Moreover, challenges are present in almost all aspects of EUVL technology. Almost all primary semiconductor manufacturing companies plan to implement commercial pre-production step-and-scan exposure tools in 2011. However, EUVL power at an intermediate focusing level has not yet met the volume manufacturing requirements. EUVL resists have been significantly improved recently, but there is still a critical need to meet requirements on resolution, line width roughness, and sensitivity. Creating a defect-free EUVL mask is another obstacle to the application of EUVL. ML2 and NIL, like EUVL, have also undergone significant progress recently, but throughput, defect control, and cost remain the critical impediments for practical application.

Bonding GaAs to Si yields highly efficient tandem solar cells. However, the use of high temperatures in heterostructure formation and native
oxides create defects that inhibit bonding.
This work uses instead low temperature Nano-Bonding™(NB) [1], via Surface Energy Engineering (SEE), to create 2D Precursor Phases leading
to a high density of molecular cross-bonds and interphase formation. SEE is based on surface energy (SE) characterization via Three Liquid
Contact Angle Analysis (3LCAA), and on composition by Ion Beam Analysis (IBA), and X-Ray Photoelectron Spectroscopy (XPS).
IBA yields absolute O coverages while XPS measures the distribution of oxidation states.
After Nano-Bonding, Surface Acoustic Wave Microscopy (SAM) and Cross-Sectional Transmission Electron Microscopy (TEM) image the bondedinterface.
SAM reveals that 98±1% of GaAs successfully nano-bonds to Si at T<220°C with compression and 48±1% bonds without compression.
TEM further reveals that both GaAs and Si are so reactive after SEE, that they oxidize very significantly without pressure applied in gaps found in
the 48±1% bonded interphase.
[1] Herbots et al. US Patents 6613677 (2003), 7,851,365 (2010), 9,018,077 (2015), 9,589,801 (2017), US patent pending (2021)
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