In computing, PSE-36 refers to a feature of x86 processors that extends the physical memory addressing capabilities from 32 bits to 36 bits. This mechanism is a simpler alternative to the Physical Address Extension (PAE) method. It uses the Page Size Extension (PSE) mode and a modified page directory table to map 4 megabyte (MB) pages into a 64 gigabyte (GiB) physical address space. PSE-36 was introduced into the x86 with the Pentium III architecture.[1]
Operation [link]
Enabling PSE alone (by setting bit 4, PSE, of the system register CR4) allows to use large 4 MiB pages along with normal 4 KiB pages.
If newer PSE-36 capability is available on the CPU, as checked using the CPUID instruction, then 4 more bits, in addition to the 10 bits used in PSE, are used inside a page directory entry pointing to a large page. This allows a large page to be located in 36 bit address space.
PAE also allows 36-bit addressing. PSE-36 has the advantages that the hierarchy of page tables is not changed, and that page entries keep their old 32-bit format and are not extended to 64 bits. The obvious disadvantage of PSE-36 is that only large pages can be located in 64 GiB of physical memory, and small pages can still be located only in the first 4 GiB of physical memory.
The PS bit (bit 7) in the Page Directory Entry (PDE) denotes whether this entry refers to a page table (that describes 1024 4-KiB pages) or one 4 MiB page. PDE structures in normal mode, PSE mode, and PSE-36 mode are as follows:
| 31-22 | 21-17 | 16-13 | 12 | 11-9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| non-PSE | base address of page table | avail | 0 | PS=0 | ign | A | PCD | PWT | U | W | P | |||||||||||||||||||||
| PSE | bit 31..22 of page frame address | reserved (must be zero) | PAT | avail | 0 | PS=1 | D | A | PCD | PWT | U | W | P | |||||||||||||||||||
| PSE-36 | bit 31..22 of page frame address | reserved (must be zero) | bit 35..32 of page frame address | PAT | avail | 0 | PS=1 | D | A | PCD | PWT | U | W | P | ||||||||||||||||||
- PAT: Page Attribute Table (since Pentium III, must be zero for older CPUs)
- D: "dirty" bit: set to 1 by CPU if there was a write access to that page. For 4 KiB pages this flag exists in the according page table entry (PTE).
AMD extends this scheme to 40 address bits by interpreting bits 20..13 of a PDE as bit 39..32 of the page base address in their AMD64 processors, so only bit 21 is reserved (must be zero).
See also [link]
References [link]
- ^ Intel 64 and IA-32 Architectures Software Developer's Manuals Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A. Intel Corporation. August, 2007. pp. 3–40 to 3-41. https://developer.intel.com/products/processor/manuals/index.htm Intel 64 and IA-32 Architectures Software Developer's Manuals. "The PSE-36 mechanism was introduced into the IA-32 architecture with the Pentium III processors."
