The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.

Overview [link]

In terms of its instruction-set architecture, MicroBlaze is very similar to the RISC-based DLX architecture described in a popular computer architecture book by Patterson and Hennessy. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances.

The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the CoreConnect PLB bus, is a traditional system-memory mapped transaction bus with master/slave capability. A newer version of the MicroBlaze, supported in both Spartan-6 and Virtex-6 implementations, as well as the 7-Series, supports the AXI specification. The majority of vendor-supplied and third-party IP interface to PLB directly (or through an PLB to OPB bus bridge.) For access to local-memory (FPGA BRAM), MicroBlaze uses a dedicated LMB bus, which reduces loading on the other buses. User-defined coprocessors are supported through a dedicated FIFO-style connection called FSL (Fast Simplex Link). The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module.

Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage or 5-stage), embedded peripherals, memory management unit, and bus-interfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock-frequency for reduced logic-area. The performance-optimized version expands the execution-pipeline to 5-stages, allowing top speeds of 210 MHz (*on Virtex-5 FPGA family.) Also, key processor instructions which are rarely used but more expensive to implement in hardware can be selectively added/removed (i.e. multiply, divide, and floating-point ops.) This customization enables a developer to make the appropriate design tradeoffs for a specific set of host hardware and application software requirements.

With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel. Otherwise it is limited to operating systems with a simplified protection and virtual memory-model: e.g. FreeRTOS or Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hardened CPU-core (such as the PowerPC440 in the Virtex-5.)

EDK [link]

Xilinx's EDK (Embedded Development Kit) is the development package for building MicroBlaze (and PowerPC) embedded processor systems in Xilinx FPGAs. Hosted in the Eclipse IDE, the project manager consists of two separate environments: XPS and SDK.

Designers use XPS (Xilinx Platform Studio) to configure and build the hardware specification of their embedded system (processor core, memory-controller, I/O peripherals, etc.) The XPS converts the designer's platform specification into a synthesizeable RTL description (Verilog or VHDL), and writes a set of scripts to automate the implementation of the embedded system (from RTL to the bitstream-file.) For the MicroBlaze core, the EDK normally generates an encrypted (non human-readable) netlist, but the processor description (written in VHDL) can be purchased from Xilinx.

The SDK handles the software that will execute on the embedded system. Powered by the GNU toolchain (GNU Compiler Collection, GNU Debugger), the SDK enables programmers to write, compile, and debug C/C++ applications for their embedded system. Xilinx includes a cycle-accurate instruction set simulator (ISS), giving programmers the choice of testing their software in simulation, or using a suitable FPGA-board to download and execute on the actual system.

Purchasers of EDK or ISE Design Suite Embedded Edition(IDS) are granted a perpetual license to use MicroBlaze in Xilinx FPGAs with no recurring royalties. The license does not grant the right to use MicroBlaze outside of Xilinx's devices, which must be negotiated directly with Xilinx.

Alternative compilers and development tools have been made available from Altium but an EDK installation and license is still required.

Open Source [link]

In June, 2009, MicroBlaze became the first soft-CPU architecture to be merged into the mainline Linux Kernel Source tree. This work was performed by Michal Simek and supported by PetaLogix and Xilinx.

In May, 2009, Edgar E. Iglesias contributed a MicroBlaze guest port for QEMU.

As of September 2009, MicroBlaze GNU tools support is also being contributed to the Free Software Foundation's mainline repositories. Support for MicroBlaze is included in GCC releases starting with version 4.6^[1]  .

Clones [link]

• aeMB, implemented in Verilog, LGPL license
• OpenFire subset, implemented in Verilog, MIT license
• MB-Lite, implemented in VHDL, LGPL license
• MB-Lite+, implemented in VHDL, LGPL license
• myBlaze, implemented in MyHDL, LGPL license
• SecretBlaze, implemented in VHDL, GPL license

Other soft processors [link]

• TSK3000
• Xtensa

See also [link]

• OpenCores - a home for many open source soft processor projects
• PicoBlaze

References [link]

1. ^ "GCC 4.6 Release Series Changes, New Features, and Fixes". 2011-03-15. https://gcc.gnu.org/gcc-4.6/changes.html#microblaze. Retrieved 2011-03-15. "Support has been added for the Xilinx MicroBlaze softcore processor (microblaze-elf) embedded target." 

External links [link]

• MicroBlaze on Xilinx website
• PetaLogix - MicroBlaze kernel maintainers and commercial services (PetaLinux)
• uCLinux - uClinux-dist for Microblaze, kernel 2.6.30
• MicroBlaze Embedded Linux support from LynuxWorks (BlueCat Linux)
• Linux and U-BOOT for Microblaze CPU - Michal Simek - maintainer
• MicroBlaze-Based Introduction To Computer Architecture and Assembly Language (UARK)
• MicroBlaze managed forum
• Running eCos RTOS on Microblaze