High Bandwidth Memory

High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked DRAM from AMD and Hynix. It is to be used in conjunction with high-performance graphics accelerators and network devices. The competing technology is the incompatible Hybrid Memory Cube interface from Micron Technology. The first devices to use HBM are the AMD Fiji GPU as well as AMD Arctic Islands-based and Nvidia Pascal-based GPUs.

High Bandwidth Memory has been adopted by JEDEC as an industry standard in October 2013.

Technology

HBM achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4 or GDDR5. This is achieved by stacking up to eight DRAM dies, including an optional base die with a memory controller, which are interconnected by through-silicon vias (TSV) and microbumps.

HBM memory bus is very wide in comparison to other DRAM memories such as DDR4 or GDDR5. An HBM stack of four DRAM dies (4-Hi) has two 128-bit channels per die for a total of 8 channels and a width of 1024 bits in total. A chip with four 4-Hi HBM stacks would therefore have a memory bus with a width of 4096 bits. In comparison, the bus width of GDDR memories is 64 bits, with 8 channels for a graphics card with a 512-bit memory interface.

HBM

HBM may refer to: