Fastbus

Fastbus was a proposed orbital, limited-stop bus service in North-West London.

It is proposed to run between Wembley Park station and North Acton station.

Proposal

The scheme is promoted by the business group Park Royal Partnership and supported by the London Borough of Brent and London Borough of Ealing. Fastbus stops might be located at:

with possible extension to Acton Main Line station.

A new road in Park Royal, near the Diageo 'First Central' business park, has been built with bus lanes, in anticipation of the new service. As of mid-2009, there has been no support for the proposal by Transport for London.

References

FASTBUS

FASTBUS (IEEE 960) is a computer bus standard, originally intended to replace CAMAC in high-speed, large-scale data acquisition. It is also a modular crate electronics standard commonly used in data acquisition systems in particle physics experiments.

Bus Description

A FASTBUS system consists of one or more segments. Each segment may be a "crate segment" or a "cable segment". Segments are connected together using a segment interconnect (SI). A crate segment typically consists of a backplane with slots to hold up to 25 modules, mounted in a 19-inch rack. Each module is typically a printed circuit board with a front panel, similar to a Blade PC. Modules are physically about 14 inches by 15 inches, and may occupy one or more adjacent slots.

Small systems may consist of only one crate segment, or a small number of independent crate segments connected directly to a central computer rather than using segment interconnects.

FASTBUS uses the Emitter coupled logic (ECL) electrical standard, which allows higher speed than TTL and generates less switching noise. Segments implement a 32-bit multiplexed address/data bus, which allows a larger address space than CAMAC. A module may be a Master or slave. There may be multiple masters in a segment; masters arbitrate for control of the bus and then perform data transfers to or from slaves. This allows for very fast read-out of an entire segment by doing a chained block read from a master with a general-purpose CPU. Each IO card will then assume mastership, send its data and then hand off mastership to the next card in a sequence, all without the overhead of the supervising board with the general-purpose CPU.