CPU multiplier

In computing, the clock multiplier (or CPU multiplier or bus/core ratio) measures the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles (produced by PLL-based frequency multiplier circuitry) for every external clock cycle. For example, a system with an external clock of 133 MHz and a 10x clock multiplier will have an internal CPU clock of 1.33 GHz. The external address and data buses of the CPU (often collectively termed front side bus or FSB in PC contexts) also use the external clock as a fundamental timing base; however, they could also employ a (small) multiple of this base frequency (typically two or four) in order to transfer data faster.

The internal frequency of microprocessors is usually based on front side bus (FSB) frequency. To calculate internal frequency the CPU multiplies bus frequency by a number called the clock multiplier. For calculation, the CPU uses actual bus frequency, and not effective bus frequency. To determine the actual bus frequency for processors that use dual-data rate (DDR) buses (AMD Athlon and Duron) and quad-data rate buses (all Intel microprocessors starting from Pentium 4) the effective bus speed should be divided by 2 for AMD or 4 for Intel.