IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Special Section on Multiple-Valued Logic and VLSI Computing
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation
Hiroki NAKAHARATsutomu SASAOMunehiro MATSUURAYoshifumi KAWAMURA
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2010 Volume E93.D Issue 8 Pages 2048-2058

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Abstract
The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary branch instructions. We realized many benchmark functions on the PBM128, and compared its memory size, computation time, and power consumption with the Intel's Core2Duo microprocessor. The PBM128 requires approximately a quarter of the memory for the Core2Duo, and is 21.4-96.1 times faster than the Core2Duo. It dissipates a quarter of the power of the Core2Duo. Also, we realized packet filters such as an access controller and a firewall, and compared their performance with software on the Core2Duo. For these packet filters, the PBM128 requires approximately 17% of the memory for the Core2Duo, and is 21.3-23.7 times faster than the Core2Duo.
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© 2010 The Institute of Electronics, Information and Communication Engineers
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