A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11 a wireless LAN standard

AR Behzad, ZM Shi, SB Anand, L Lin… - IEEE Journal of Solid …, 2003 - ieeexplore.ieee.org
A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control
is implemented in a 0.18-μm digital CMOS process and housed in an LPCC-48 package. …

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

SB Anand, B Razavi - IEEE journal of solid-state circuits, 2002 - ieeexplore.ieee.org
This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-/spl
mu/m digital CMOS technology. To achieve a high speed with low power dissipation, a …

[BOOK][B] High-speed clock and data recovery circuits for random non-return-to-zero data

SB Anand - 2001 - search.proquest.com
… Thiara, Iqbal Bhatti, and Vivek Anand. A special thanks goes to my parents Sudha and
Anil Butala and Usha and Narinder Anand for their continuous support and encouragement …

A 2.75 Gb/s CMOS clock recovery circuit with broad capture range

SB Anand, B Razavi - … Solid-State Circuits Conference. Digest of …, 2001 - ieeexplore.ieee.org
A dual-loop PLL clock-recovery circuit uses a digital search algorithm to increase capture
range with no external reference. A 0.25/spl mu/m CMOS circuit has 350 MHz capture range …

A low-power single-weight-combiner 802.11 abg SoC in 0.13 µm CMOS for embedded applications utilizing an area and power efficient Cartesian phase shifter and …

…, M Pan, S Au, A Ojo, CP Lee, SB Anand… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest
reported power consumption and utilizes an extensive array of auto calibrations is reported. …

A fully integrated SOC for 802.11 b in 0.18-/spl mu/m CMOS

…, J Castaneda, HM Chien, SB Anand… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in
0.18-/spl mu/m CMOS. All of the radio building blocks including the power amplifier (PA), …

A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-/spl mu/m CMOS technology

SB Anand, B Razavi - Proceedings of the IEEE 2000 Custom …, 2000 - ieeexplore.ieee.org
This paper describes a 2.5-Gb/s phase-locked clock recovery circuit utilizing a two-stage
ring oscillator and a sample-and-hold phase detector. Fabricated in a 0.4-/spl mu/m digital …

Performance studies of the dual loop clock and data recovery circuits in the presence of power supply noise

PV Ramakrishna - shodhganga.inflibnet.ac.in
… by Seema Butala Anand et al an architecture which is considered as one of the important
alternatives available for implementing CDR circuits A systematic newlinesimulation study has …

A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

DP Bautista, FRC Soria, ML Aranda… - Ingeniería e …, 2007 - revistas.unal.edu.co
The clock recovery circuit (CRC) plays a fundamental role in electronic information recovery
systems (hard disks, DVD and CD read/writeable units) and baseband digital …

[HTML][HTML] Circuito de recuperación de reloj CMOS completamente integrable, diferencial, de alta velocidad y bajo consumo de potencia

D Pacheco Bautista, FR Castillo Soria… - Ingeniería e …, 2007 - scielo.org.co
En los sistemas electrónicos de recuperación de información (discos duros, unidades de
lectura y escritura de DVD y CD, etc.), así como en las comunicaciones digitales en banda …