Hardware accelerators are getting increasingly important in heterogeneous systems for
many applications, including those that employ matrix decompositions. In recent years, a
class of tiled matrix decomposition algorithms has been proposed for out-of-memory
computations and multi-core architectures including GPU-based heterogeneous systems.
However, on FPGAs these scalable solutions for large matrices are rarely found. In this
paper we use the latest tiled decomposition algorithms from high performance linear algebra …