Recently, due to remarkable technological developments and because their logic can be modified flexibly and easily, Field Programmable Gate Arrays (FPGAs) have increasingly been applied to hardware prototyping and the design of restructurable computer architectures. For this reason, it is highly necessary to establish logic design techniques for FPGAs.

This paper describes methods for optimizing the circuits mapped in look‐up table‐type FPGAs. These methods apply the concept of permissible functions from the transduction method, which is a logic circuit optimization technique based on design improvement, and attempt to reduce the degree of redundancy. The following two methods were investigated: 1) reducing the number of blocks by using a logic block to replace another; and 2) together with replacing logic blocks, modifying the internal logic that implements a logic block as long as the outputs are not affected. Although the latter generally is more flexible, the former requires less processing time and sometimes produces better results. The effectiveness of these methods is demonstrated by showing that the degree of redundancy was reduced by about 9 percent when the methods were applied to circuits mapped in look‐up table‐type FPGAs. The methods proposed in this paper can also be applied to designs using standard cells and gate arrays.