Nonenumerative path delay fault coverage estimation with optimal algorithms
D Kagaris, S Tragoudas… - … Conference on Computer …, 1997 - ieeexplore.ieee.org
D Kagaris, S Tragoudas, D Karayiannis
Proceedings International Conference on Computer Design VLSI in …, 1997•ieeexplore.ieee.orgA recent method proposed that a lower bound on the number of path delay faults excited by
a given test set can be computed using a set independent lines that form a cut. For each line
in the cut a subcircuit consisting of all paths that contain the line is defined, and a lower
bound to the number of excited path delay faults can be obtained by working on the
respective subcircuits. A polynomial time algorithm is presented here for computing the
maximum cardinality set of independent circuit lines. Experimental results show that the …
a given test set can be computed using a set independent lines that form a cut. For each line
in the cut a subcircuit consisting of all paths that contain the line is defined, and a lower
bound to the number of excited path delay faults can be obtained by working on the
respective subcircuits. A polynomial time algorithm is presented here for computing the
maximum cardinality set of independent circuit lines. Experimental results show that the …
A recent method proposed that a lower bound on the number of path delay faults excited by a given test set can be computed using a set independent lines that form a cut. For each line in the cut a subcircuit consisting of all paths that contain the line is defined, and a lower bound to the number of excited path delay faults can be obtained by working on the respective subcircuits. A polynomial time algorithm is presented here for computing the maximum cardinality set of independent circuit lines. Experimental results show that the more the subcircuits the better the lower bound on the number of excited path delay faults is. More subcircuits may be generated only in a heuristic manner. It was proposed to consider two or more line-disjoint cuts C/sub i/. We propose a technique where only one C/sub i/ must be a cut. This scheme is based on novel algorithms, and results in more subcircuits than the previous one.
ieeexplore.ieee.org
Showing the best result for this search. See all results