[PDF][PDF] Minimal delay interconnect design using alphabetic trees
A Vittal, M Marek-Sadowska - Proceedings of the 31st Annual Design …, 1994 - dl.acm.org
A Vittal, M Marek-Sadowska
Proceedings of the 31st Annual Design Automation Conference, 1994•dl.acm.orgWe propose a new algorithm for the performancedriven interconnect design problem, based
on alphabetic trees. The interconnect topology is determined in a global manner and does
not greedily add edges as in conventional approaches. The algorithm can handle cases
where the sink capacitances are different. Good results are obtained while running two to
sixty times faster than three existing algorithms on practical instances.
on alphabetic trees. The interconnect topology is determined in a global manner and does
not greedily add edges as in conventional approaches. The algorithm can handle cases
where the sink capacitances are different. Good results are obtained while running two to
sixty times faster than three existing algorithms on practical instances.
Abstract
We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner and does not greedily add edges as in conventional approaches. The algorithm can handle cases where the sink capacitances are different. Good results are obtained while running two to sixty times faster than three existing algorithms on practical instances.
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