A wrapper is a thin shell around the core, that provides the switching between functional,
and core-internal and core-external test modes. Together with a test access mechanism (TAM), …

The main objective of core-based IC design is improvement of design efficiency and time-to-market.
In order to prevent test development from becoming the bottleneck in the entire …

This defect-based study analyzes statistical signal delay properties and delay fault test pattern
constraints in the CMOS deep submicron environment. Delay fault testing has uncertainty, …

The increased usage of embedded pre-designed reusable cores necessitates a core-based
test strategy, in which cores are tested as separate entities. IEEE P1500 Standard for …

The ability to achieve and maintain high yield levels depends on the capability of detecting,
analyzing and correcting repetitive failure mechanisms. In this paper, a statistical fault …

This paper reflects on some recent results that show the value of delay-fault tests on a deep
sub-micron process. However, the results also suggest that untargetted test patterns perform …

As part of an industry wide effort the IEEE is in the process of standardizing the elements of
test technology such that plug & play can be achieved when testing SoC designs. This …

A core-based design style introduces new test challenges, which, if not dealt with properly,
might defeat the entire purpose of using pre-designed cores. Macro Test is a liberal test …

A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS
circuits is presented. The defective line is first classified as fully opened by means of a logic-…

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield
improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this …