User profiles for Joseph B. Bernstein

Joseph Bernstein

Ariel University
Verified email at ariel.ac.il
Cited by 4341

Compact modeling of MOSFET wearout mechanisms for circuit-reliability simulation

X Li, J Qin, JB Bernstein - IEEE Transactions on device and …, 2008 - ieeexplore.ieee.org
The integration density of state-of-the-art electronic systems is limited by the reliability of the
manufactured integrated circuits at a desired circuit density. Design rules, operating voltages…

Electronic circuit reliability modeling

JB Bernstein, M Gurfinkel, X Li, J Walters… - Microelectronics …, 2006 - Elsevier
The intrinsic failure mechanisms and reliability models of state-of-the-art MOSFETs are
reviewed. The simulation tools and failure equivalent circuits are described. The review includes …

Characterization of Transient Gate Oxide Trapping in SiC MOSFETs Using Fast Techniques

…, KP Cheung, JS Suehle, JB Bernstein… - … on Electron Devices, 2008 - ieeexplore.ieee.org
Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with
thermal as-grown SiO 2 and NO-annealed gate oxides have been studied using fast IV …

Time-Dependent Dielectric Breakdown of 4H-SiC/ MOS Capacitors

…, JC Horst, JS Suehle, JB Bernstein… - IEEE transactions on …, 2008 - ieeexplore.ieee.org
Time-dependent dielectric breakdown (TDDB) is one of the major issues concerning long-range
reliability of dielectric layers in SiC-based high-power devices. Despite the extensive …

[HTML][HTML] Modern trends in microelectronics packaging reliability testing

E Bender, JB Bernstein, DS Boning - Micromachines, 2024 - mdpi.com
In this review, recent trends in microelectronics packaging reliability are summarized. We
review the technology from early packaging concepts, including wire bond and BGA, to …

Spatial distributions of trapping centers in HfO2∕ SiO2 gate stacks

…, A Diebold, G Bersuker, EM Vogel, JB Bernstein - Applied physics …, 2006 - pubs.aip.org
A methodology to analyze charge pumping (CP) data, which allows positions of probing traps
in the dielectric to be identified, was applied to extract the spatial profile of traps in SiO 2∕ …

Reliability simulation and circuit-failure analysis in analog and mixed-signal applications

…, J Qin, J Dai, Q Fan, JB Bernstein - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
In this paper, an effective and efficient methodology for reliability simulation is developed to
bridge the gap between device-level reliability and that at product level. For the first time, …

Failure dynamics of the IGBT during turn-off for unclamped inductive loading conditions

…, AR Hefner, DW Berning, JB Bernstein - IEEE Transactions on …, 2000 - ieeexplore.ieee.org
The internal failure dynamics of the insulated gate bipolar transistor (IGBT) for unclamped
inductive switching (UIS) conditions are studied using simulations and measurements. The …

[BOOK][B] Thomas Jefferson

RB Bernstein - 2005 - books.google.com
… It is in this simple epitaph that RB Bernstein finds the key to this … , Bernstein offers the
definitive short biography of this revered American--the first concise life in six decades. Bernstein

A new SPICE reliability simulation method for deep submicrometer CMOS VLSI circuits

…, B Huang, X Zhang, JB Bernstein - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
CMOS very large scale integration (VLSI) circuit reliability modeling and simulation have
attracted an intense research interest in the last two decades, and as a result, almost all IC …