Defect analysis and cost-effective resilience architecture for future DRAM devices
…, K Park, SJ Jang, JS Choi, GY Jin… - … Symposium on High …, 2017 - ieeexplore.ieee.org
Technology scaling has continuously improved the density, performance, energy efficiency,
and cost of DRAM-based main memory systems. Starting from sub-20nm processes, …
and cost of DRAM-based main memory systems. Starting from sub-20nm processes, …
Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)
…, YC Oh, Y Hwang, H Hong, GY Jin… - 2011 Proceedings of …, 2011 - ieeexplore.ieee.org
New 4F 2 cell structure of VPT for the future DRAM devices has been successfully developed
by using 30nm process technology. The VPT shows superior current driving capability of …
by using 30nm process technology. The VPT shows superior current driving capability of …
A 31 ns Random Cycle VCAT-Based 4F DRAM With Manufacturability and Enhanced Cell Efficiency
…, D Park, WS Kim, YT Lee, YC Oh, GY Jin… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
A functional 4F 2 DRAM was implemented based on the technology combination of stack
capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance …
capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance …
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme
…, JH Choi, KI Park, SJ Jang, GY Jin - … Solid-State Circuits …, 2017 - ieeexplore.ieee.org
With growing demand for low-power mobile applications, such as wearable devices, smart
phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory …
phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory …
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution
…, SB Ko, KI Park, SJ Jang, GY Jin - … Solid-State Circuits …, 2016 - ieeexplore.ieee.org
A 9Gb/s/pin 8Gb GDDR5 DRAM is implemented using a 20nm CMOS process. To cover
operation up to 9Gb/s, which is the highest data-rate among implemented GDDR5 DRAMs [1], …
operation up to 9Gb/s, which is the highest data-rate among implemented GDDR5 DRAMs [1], …
23.4 An extremely low-standby-power 3.733 Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices
…, JH Choi, KI Park, SJ Jang, GY Jin - … Solid-State Circuits …, 2017 - ieeexplore.ieee.org
With the growth of wearable devices, such as smart watches and smart glasses, there is an
increasing demand for lower power dissipation, to achieve longer battery life with limited …
increasing demand for lower power dissipation, to achieve longer battery life with limited …
Extracting mobility degradation and total series resistance of cylindrical gate-all-around silicon nanowire field-effect transistors
…, KH Cho, KH Yeo, DW Kim, GY Jin… - IEEE electron device …, 2009 - ieeexplore.ieee.org
The mobility-degradation factor and the series resistance of cylindrical gate-all-around silicon
nanowire field-effect transistors are extracted using the same mobility-degradation model …
nanowire field-effect transistors are extracted using the same mobility-degradation model …
Charge trapping induced DRAM data retention time degradation under wafer-level burn-in stress
HW Seo, GY Jin, KH Yang, YJ Lee… - … . 40th Annual (Cat …, 2002 - ieeexplore.ieee.org
This paper investigates the effects of wafer burn-in on the degradation of DRAM data retention
time characteristics. The problem was characterized using a substrate electron injection …
time characteristics. The problem was characterized using a substrate electron injection …
Considerations on highly scalable and easily stackable phase change memory cell array for low-cost and high-performance applications
…, GT Jeong, DH Ahn, SW Nam, GY Jin… - 2014 14th Annual …, 2014 - ieeexplore.ieee.org
Needs for the performance improvement of memory subsystem in big data and clouding
computing era begin to open new markets for emerging memories such as phase change …
computing era begin to open new markets for emerging memories such as phase change …
Novel Deep Trench Buried-Body-Contact (DBBC) of 4F2 cell for sub 30nm DRAM technology
…, D Kim, J Kim, Y Oh, H Hong, GY Jin… - 2012 Proceedings of …, 2012 - ieeexplore.ieee.org
Novel Deep Trench Buried-Body-Contact (DBBC) has been successfully developed for 4F 2
DRAM cells on sub-30nm technology node. The critical requirements of thermal stability, …
DRAM cells on sub-30nm technology node. The critical requirements of thermal stability, …