Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs
M Tranchero, LM Reyneri - 2009 International Conference on …, 2009 - ieeexplore.ieee.org
M Tranchero, LM Reyneri
2009 International Conference on Field Programmable Logic and …, 2009•ieeexplore.ieee.orgThis paper describes an approach to the placement of self-timed circuits onto commercial
FPGAs, using only conventional synchronous tools available on the market. Different parts of
the design are constrained in order to maintain the timing relationship required for
guaranteeing the correct circuit functionality and to keep the wiring influence on system
delays bounded and fixed across the different iterations. This work is part of the extension to
the CodeSimulink co-design environment we made in order to allow the synthesis of …
FPGAs, using only conventional synchronous tools available on the market. Different parts of
the design are constrained in order to maintain the timing relationship required for
guaranteeing the correct circuit functionality and to keep the wiring influence on system
delays bounded and fixed across the different iterations. This work is part of the extension to
the CodeSimulink co-design environment we made in order to allow the synthesis of …
This paper describes an approach to the placement of self-timed circuits onto commercial FPGAs, using only conventional synchronous tools available on the market. Different parts of the design are constrained in order to maintain the timing relationship required for guaranteeing the correct circuit functionality and to keep the wiring influence on system delays bounded and fixed across the different iterations. This work is part of the extension to the CodeSimulink co-design environment we made in order to allow the synthesis of asynchronous circuits from Simulink specifications.
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