Experiences with soft-core processor design
F Plavec, B Fort, ZG Vranesic… - 19th IEEE International …, 2005 - ieeexplore.ieee.org
F Plavec, B Fort, ZG Vranesic, SD Brown
19th IEEE International Parallel and Distributed Processing Symposium, 2005•ieeexplore.ieee.orgSoft-core processors exploit the flexibility of field programmable gate arrays (FPGAs) to
allow a system designer to customize the processor to the needs of a target application. This
paper describes the UT Nios implementation of Altera's Nios architecture. A benchmark set
appropriate for soft-core processors is defined. Using the benchmark set, the performance of
UT Nios is explored and compared with the commercial implementation.
allow a system designer to customize the processor to the needs of a target application. This
paper describes the UT Nios implementation of Altera's Nios architecture. A benchmark set
appropriate for soft-core processors is defined. Using the benchmark set, the performance of
UT Nios is explored and compared with the commercial implementation.
Soft-core processors exploit the flexibility of field programmable gate arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera's Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.
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