A wide range of vulnerabilities actively threatens the security of the integrated circuit (IC) supply chain. Logic encryption and camouflaging are two techniques that can provide significant protection against these threats. Despite the fact that researchers have proposed a large number of encryption methods over the last decade, many of them have not been thoroughly tested against a variety of benchmarks and do not provide a significant output corruption rate (OCR) and error rate (ER). OCR analysis, which relies on circuit characterization, is currently unavailable. This research analyzes OCR for various types of synthetic circuits. Two approaches for selecting circuit nodes to encrypt and camouflage are proposed based on circuit characterization. This technique is enhanced by integrating the giant spin-hall effect (GSHE) switch to combine logic encryption and dynamic camouflaging. Furthermore, the node selection methodology based on circuit characteristics lays the groundwork to achieve high OCR and ER for some specific circuit types. The proposed scheme achieves an exceptional 99.99% ER and offers the potential to achieve an OCR range of 14.32% to 45.80% through circuit categorization.