Design optimization for robustness to single-event upsets
Q Zhou, MR Choudhury… - 24th IEEE VLSI Test …, 2006 - ieeexplore.ieee.org
Q Zhou, MR Choudhury, K Mohanram
24th IEEE VLSI Test Symposium, 2006•ieeexplore.ieee.orgAn optimization algorithm for the design of combinational circuits that are robust to single-
event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of
a logic gate is developed. This model is integrated with area and performance constraints
into an optimization framework based on geometric programming for design space
exploration. Simulation results demonstrate the design tradeoffs that can be achieved with
this approach.
event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of
a logic gate is developed. This model is integrated with area and performance constraints
into an optimization framework based on geometric programming for design space
exploration. Simulation results demonstrate the design tradeoffs that can be achieved with
this approach.
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model is integrated with area and performance constraints into an optimization framework based on geometric programming for design space exploration. Simulation results demonstrate the design tradeoffs that can be achieved with this approach.
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