The proposed work presents a co-design approach for a new asymmetric rectangular cross shaped slotted patch antenna with low noise amplifier that occupies 17.2–25.8 GHz wide-band for SDR applications. This co-design approach minimizes the chip area and noise and also improves integration system over the bandwidth of 8.6 GHz. Three different architectures have been designed in this work. Firstly, a two stage CMOS CG–CS LNA is designed using a technique of series–parallel resonant network as an input matching network and as inter-stage matching network between CG and CS LNA. In second architecture stage, a rectangular shaped microstrip antenna is designed and a slot of asymmetric cross shape is cut on the patch antenna. In third architecture the slotted antenna is integrated with low noise amplifier in order to form a co-design approach in which series–parallel resonant network is used as a band pass filter between slotted patch antenna and LNA. A two-stage CMOS LNA design is simulated and layout is made using foundry design kit for the TSMC 65 nm CMOS process in ADS.v.12. A simulation result of LNA achieves S₁₁ of −21.4 dB with gain ranging from 7.4 to 21.3 dB over the wide-band of 19.1–28.8 GHz. The slotted antenna achieves S₁₁ of −19 dB at 26 GHz and covers frequency range of 20.1–27.8 GHz with good radiation and receiving patterns. This co-design approach is analysed considering the 50 Ω impedance matching throughout the design and simulated on the platform of ADS.v.12. The best achievement of proposed co-design approach is reduced noise figure which is most suitable for SDR applications.