An 8.8 GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS
S Hsu, A Agarwal, M Anders, S Mathew… - … Solid State Circuits …, 2006 - ieeexplore.ieee.org
2006 IEEE International Solid State Circuits Conference-Digest of …, 2006•ieeexplore.ieee.org
A 16X64b 1R/1W register file is fabricated in 65nm CMOS technology. The 0.017 mm 2 chip
performs 8.8 GHz fused decode and read/write operations in a single cycle while dissipating
198mW at 1.2 V, 50° C, with frequency scalable to 10.1 GHz at 1.4 V, 50degC. Variation-
tolerant keeper compensation, leakage-tolerant BL/WL architecture and optimal non-
minimum channel-length usage enable wide PVT operating range with an active leakage of
25mW and a BL noise droop les8mV
performs 8.8 GHz fused decode and read/write operations in a single cycle while dissipating
198mW at 1.2 V, 50° C, with frequency scalable to 10.1 GHz at 1.4 V, 50degC. Variation-
tolerant keeper compensation, leakage-tolerant BL/WL architecture and optimal non-
minimum channel-length usage enable wide PVT operating range with an active leakage of
25mW and a BL noise droop les8mV
A 16X64b 1R/1W register file is fabricated in 65nm CMOS technology. The 0.017mm 2 chip performs 8.8GHz fused decode and read/write operations in a single cycle while dissipating 198mW at 1.2V, 50°C, with frequency scalable to 10.1GHz at 1.4V, 50degC. Variation-tolerant keeper compensation, leakage-tolerant BL/WL architecture and optimal non-minimum channel-length usage enable wide PVT operating range with an active leakage of 25mW and a BL noise droop les8mV
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