This paper proposes a pipeline programmable interleaved baseband circuitry for modern Global Navigation Satellite Systems (GNSSs) signals. The involvement of new GNSSs leads to the requirement of designing a programmable multi-GNSS baseband receiver that can be reconfigured across GNSS signals. The baseband circuit parallelism is the easiest approach, but resource consumption will be significant. Hardware time multiplexing is more effective technique. However, it requires an efficient memory hierachy and an efficient design. These challenges are tackled in the proposed architecture which utilises as 3.2%, 6.6%, 12.5% and 50% resources as the conventional baseband circuitry consisting of 16 GPS L1 C/A channels, 8 BEIDOU B1I channels, 4 GALILEO E1 channels, and 1 GPS L5 channel, respectively. The power consumption is also reduced by 29% to 70% compared to the corresponding conventional digital correlator circuits; while it is still meeting the timing constrain of the baseband receiver.