A PA-RISC microprocessor PA/50L for low-cost systems
T Okada, S Narita, O Nishii, N Hiratsuka… - … of COMPCON'94, 1994 - ieeexplore.ieee.org
T Okada, S Narita, O Nishii, N Hiratsuka, N Hayashi, M Asai, S Fujiwara, M Satoh…
Proceedings of COMPCON'94, 1994•ieeexplore.ieee.orgThe PA/50L is a low-cost, low-power microprocessor from Hitachi Ltd. that is fully compatible
with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS
(Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to
achieve high performance with no external cache, a non-blocking cache and a data prefetch
instruction are provided. This paper gives an overview of the microprocessor and describes
its capabilities.<>
with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS
(Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to
achieve high performance with no external cache, a non-blocking cache and a data prefetch
instruction are provided. This paper gives an overview of the microprocessor and describes
its capabilities.<>
The PA/50L is a low-cost, low-power microprocessor from Hitachi Ltd. that is fully compatible with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS (Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to achieve high performance with no external cache, a non-blocking cache and a data prefetch instruction are provided. This paper gives an overview of the microprocessor and describes its capabilities.< >
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