Automated Wiring Analysis of Integrated Circuit Geometric Data

Citation

Lang, Charles Richard (1979) Automated Wiring Analysis of Integrated Circuit Geometric Data. Master's thesis, California Institute of Technology. doi:10.7907/qxbg-2c10. https://resolver.caltech.edu/CaltechThesis:03092018-151643742

Abstract

Methods are presented by which wiring data of an NMOS integrated circuit may be extracted from its mask information. The procedures involved utilize the capabilities of a general purpose polygon package. The polygon operations are defined to enhance their use in this application, however the package is suitable for other uses such as, design rule checking. The analysis is performed on hierarchical symbol definitions of mask geometry. The geometry is presumed to be described in CIF 2.0 (Caltech Intermediate Form). The analysis attempts to recognize three basic types of structures in the geometry:

1) Transistor devices (and capacitors)
2) Local interconnection structures and
3) Global interconnection structures

Definitions are put forth for the distinction of global and local wires. The data extracted from the symbol geometry is the percent utilization of each symbol's area by each of the three types of structures. The purpose behind the extraction of this data is its use in the development and evaluation of wiring models for custom NMOS IC design. Two approaches are presented which extract such data. The first is heuristic and depends on built-in assumptions of how the NMOS process is generally used. This technique loses accuracy if a design style falls outside of these assumptions. The second technique is a method by which the topology of design may be extracted from the geometry. The geometric objects, from which devices and interconnections are made, are preserved, such that the wiring information can be obtained precisely. This method is complex and requires considerable computation, however, the topology extracted may also be used to verify the geometric data against the original design topology.

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