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good first issuehttps://github.com/llvm/llvm-project/contributehttps://github.com/llvm/llvm-project/contributellvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passesmissed-optimization
Description
The following transformation is legal after adding nneg
:
define i32 @src(i8 %v) {
%switch.tableidx = add nsw i8 %v, 1
%switch.idx.cast = zext nneg i8 %switch.tableidx to i32
%switch.offset = add nsw i32 %switch.idx.cast, -1
ret i32 %switch.offset
}
define i32 @tgt(i8 %v) {
%ext = sext i8 %v to i32
ret i32 %ext
}
Alive2: https://alive2.llvm.org/ce/z/2iCmDs
From: rust-lang/rust#106459 (comment)
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good first issuehttps://github.com/llvm/llvm-project/contributehttps://github.com/llvm/llvm-project/contributellvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passesmissed-optimization